Commit 422c6170 authored by Marijam Schmidt's avatar Marijam Schmidt
Browse files

add ball

parent 5fab2cf5
......@@ -16,6 +16,7 @@ SYN_SOURCE_FILES = \
../../src/vsyncgen_rtl.vhd \
../../src/de1_vga_rtl.vhd \
../../src/hsyncgen_rtl.vhd \
../../src/ball_rtl.vhd \
../../src/t_de1_vga.vhd
# do not delete this line
......
......@@ -7,6 +7,8 @@ entity bildgen is
hpixel : in std_ulogic_vector(9 downto 0);
vactive : in std_ulogic;
hactive : in std_ulogic;
ballX : in std_ulogic_vector(9 downto 0);
ballY : in std_ulogic_vector(9 downto 0);
VGA_R : out std_ulogic_vector(3 downto 0);
VGA_G : out std_ulogic_vector(3 downto 0);
VGA_B : out std_ulogic_vector(3 downto 0));
......@@ -14,25 +16,35 @@ end entity bildgen;
architecture rtl of bildgen is
signal active : std_ulogic;
signal pixel, zeile : unsigned(9 downto 0);
signal pixel, zeile, x, y, ballH, ballW : unsigned(9 downto 0);
begin
active <= (hactive and vactive);
x <= unsigned(ballX);
y <= unsigned(ballY);
ballH <=y+20;
ballW <=x+20;
pixel <= unsigned(hpixel);
zeile <= unsigned(vpixel);
process(pixel, zeile, active)
process(pixel, zeile, active, x,y,ballH,ballW)
begin
if(active = '1')then
if ((pixel > x )and (pixel <= ballW)and (zeile > y)and (zeile <= ballH))then
VGA_R <= "0000";
VGA_G <= "1111";
VGA_B <= "0000";
else
VGA_R <= "1111";
VGA_G <= "0000";
VGA_B <= "1111";
else
VGA_R <= "0000";
VGA_G <= "0000";
VGA_B <= "0000";
end if;
end process;
end architecture rtl;
l
\ No newline at end of file
VGA_B <= "0000";
end if;
else
VGA_R <= "0000";
VGA_G <= "0000";
VGA_B <= "0000";
end if;
end process;
end architecture rtl;
\ No newline at end of file
......@@ -45,15 +45,30 @@ component bildgen is
hpixel : in std_ulogic_vector (9 downto 0);
vactive : in std_ulogic;
hactive : in std_ulogic;
ballX : in std_ulogic_vector(9 downto 0);
ballY : in std_ulogic_vector(9 downto 0);
VGA_R : out std_ulogic_vector(3 downto 0);
VGA_G : out std_ulogic_vector(3 downto 0);
VGA_B : out std_ulogic_vector(3 downto 0));
end component bildgen;
component ball is
port (
clk_i : in std_ulogic; --50Mhz
res_n : in std_ulogic;
vdone : in std_ulogic; --dass Ball nicht zerschnitten wird
hactive : in std_ulogic;
vactive : in std_ulogic;
xball : out std_ulogic_vector(9 downto 0);
yball : out std_ulogic_vector(9 downto 0));
end component ball;
--Internal signals for forwarding between components
signal en_25Mhz, res_n, en_vsync, hactive, vactive, vdone_t: std_ulogic;
signal hpixel : std_ulogic_vector (9 downto 0);
signal vpixel : std_ulogic_vector (9 downto 0);
signal hpixel : std_ulogic_vector(9 downto 0);
signal vpixel : std_ulogic_vector(9 downto 0);
signal xball : std_ulogic_vector(9 downto 0);
signal yball : std_ulogic_vector(9 downto 0);
begin
......@@ -92,7 +107,20 @@ port map(
VGA_G => VGA_G,
VGA_B => VGA_B,
vactive => vactive,
hactive => hactive);
hactive => hactive,
ballX => xball,
ballY => yball);
ball_i0: ball
port map(
clk_i => CLOCK_50,
res_n =>SW(0),
vdone =>vdone_t,
hactive =>hactive,
vactive =>vactive,
xball => xball,
yball => yball);
LEDR <= SW;
......
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