Commit 778a3928 authored by root's avatar root
Browse files

zweite Änderung der Datei mclk.vhd

Signial a hinzugefügt
parent 4d647c2c
......@@ -11,7 +11,7 @@ entity adder is
y_o : out std_ulogic_vector(11 downto 0)
);
end;
signal a:std_ulogic;
architecture rtl of adder is
begin
......
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