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## ----------------------------------------------------------------------------
## Script     : makefile.sources
## ----------------------------------------------------------------------------
## Author     : Johann Faerber
## Company    : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
##              Attention !!!
##              -------------
##              Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------

SYN_SOURCE_FILES = \
../../src/sequence_detector_18bit.vhd \
../../src/lfsr_18bit.vhd \
../../src/cntupen_rtl.vhd

# do not delete this line
# -----------------------------------------------------------------------------