heartbeat_gen_rtl.vhd 1.71 KB
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-------------------------------------------------------------------------------
-- Module     : heartbeat_gen_rtl
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions  : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY heartbeat_gen IS
  PORT (clk_i       : IN  std_ulogic;
        rst_ni      : IN  std_ulogic;
        en_pi       : IN  std_ulogic;
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        count_o     : OUT std_ulogic_vector(9 DOWNTO 0);
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        heartbeat_o : OUT std_ulogic
        );
END heartbeat_gen;

ARCHITECTURE rtl OF heartbeat_gen IS

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  SIGNAL mux_control   : std_ulogic;
  SIGNAL next_state    : unsigned(9 DOWNTO 0);
  SIGNAL current_state : unsigned(9 DOWNTO 0);
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BEGIN

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  incrementer : next_state <= current_state + 1 WHEN mux_control = '0' ELSE to_unsigned(0, current_state'length);
  
  state_register : current_state <= to_unsigned(0, current_state'length)  WHEN rst_ni = '0' ELSE
                                    next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
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  counter_output : count_o <= std_ulogic_vector(current_state);
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  heartbeat_output : heartbeat_o <= '0' WHEN current_state <= to_unsigned(433, current_state'length) OR (current_state > to_unsigned(533, current_state'length) AND current_state <= to_unsigned(673, current_state'length))
                                    OR current_state = to_unsigned(833, current_state'length) ELSE '1';
  
  mux_control_signal : mux_control <= '1' WHEN current_state = to_unsigned(833, current_state'length) ELSE '0';
                                   
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END rtl;