t_sequence_detector.vhd 2.99 KB
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-------------------------------------------------------------------------------
-- Module     : 
-------------------------------------------------------------------------------
-- Author     :   <johann.faerber@hs-augsburg.de>
-- Company    : University of Applied Sciences Augsburg
-- Copyright (c) 2021   <johann.faerber@hs-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "sequence_detector"
-------------------------------------------------------------------------------
-- Revisions  : see end of file
-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-------------------------------------------------------------------------------

ENTITY t_sequence_detector IS

END ENTITY t_sequence_detector;

-------------------------------------------------------------------------------

ARCHITECTURE tbench OF t_sequence_detector IS

  COMPONENT sequence_detector IS
    PORT (
      clk    : IN  std_ulogic;
      rst_n  : IN  std_ulogic;
      ser_i  : IN  std_ulogic;
      done_o : OUT std_ulogic);
  END COMPONENT sequence_detector;

  COMPONENT lfsr_fibonacci IS
    PORT (
      clk_i   : IN  std_ulogic;
      rst_ni  : IN  std_ulogic;
      en_pi   : IN  std_ulogic;
      lfsr_o  : OUT std_ulogic_vector(3 DOWNTO 0);
      noise_o : OUT std_ulogic;
      eoc_po  : OUT std_ulogic);
  END COMPONENT lfsr_fibonacci;

  -- component ports
  SIGNAL clk_i    : std_ulogic;
  SIGNAL rst_ni   : std_ulogic;
  SIGNAL done_o   : std_ulogic;
  SIGNAL noise_o  : std_ulogic;
  SIGNAL eoc_po   : std_ulogic;
  SIGNAL en_pi    : std_ulogic;
  SIGNAL lfsr_o   : std_ulogic_vector(3 DOWNTO 0);


  -- definition of a clock period
  CONSTANT period : time    := 20 ns;
  -- switch for clock generator
  SIGNAL clken_p  : boolean := true;

BEGIN  -- ARCHITECTURE tbench

  -- component instantiation
  DUT : sequence_detector
    PORT MAP (
      clk    => clk_i,
      rst_n  => rst_ni,
      ser_i  => noise_o,
      done_o => done_o);

  LFSR : lfsr_fibonacci
    PORT MAP (
      clk_i   => clk_i,
      rst_ni  => rst_ni,
      en_pi   => en_pi,
      lfsr_o  => lfsr_o,
      noise_o => noise_o,
      eoc_po  => eoc_po);

  -- clock generation
  clock_p : PROCESS
  BEGIN
    WHILE clken_p LOOP
      clk_i <= '0'; WAIT FOR period/2;
      clk_i <= '1'; WAIT FOR period/2;
    END LOOP;
    WAIT;
  END PROCESS;

  -- initial reset, always necessary at the beginning OF a simulation
  reset : rst_ni <= '0', '1' AFTER period;

  -- process for stimuli generation
  stimuli_p : PROCESS


  BEGIN

    WAIT UNTIL rst_ni = '1';            -- wait until asynchronous reset ...
    en_pi <= '1';                              -- ... is deactivated
                                  


    WAIT FOR 100*period;




    clken_p <= false;                   -- switch clock generator off

    WAIT;
  END PROCESS;



END ARCHITECTURE tbench;

-------------------------------------------------------------------------------