Commit 00520ad2 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab#6: extending calculator part 1: finished

parent bd0eb2c4
......@@ -19,6 +19,7 @@ set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
......
......@@ -47,7 +47,8 @@ PROGFILEEXT = sof
# Add the toplevel fpga vhdl file
SOURCE_FILES = ../../src/$(PROJECT)_structure.vhd \
../../src/de1_binto7segment_structure.vhd \
../../src/binto7segment_truthtable.vhd
../../src/binto7segment_truthtable.vhd \
../../src/twosc2sm_rtl.vhd
include ../makefile
......
......@@ -15,7 +15,7 @@ USE IEEE.numeric_std.ALL;
ENTITY de1_calculator IS
PORT (
SW : IN std_ulogic_vector(7 DOWNTO 0); -- Toggle Switch[7:0]
LEDR : OUT std_ulogic_vector(7 DOWNTO 0); -- LED Red[7:0]
LEDR : OUT std_ulogic_vector(8 DOWNTO 0); -- LED Red[7:0]
HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0
);
END de1_calculator;
......@@ -28,15 +28,23 @@ ARCHITECTURE structure OF de1_calculator IS
segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
END COMPONENT;
SIGNAL a : unsigned(3 DOWNTO 0);
SIGNAL b : unsigned(3 DOWNTO 0);
SIGNAL sum : unsigned(3 DOWNTO 0);
COMPONENT twosc2sm
PORT (
value_sc_i : IN std_ulogic_vector(3 DOWNTO 0);
value_sm_o : OUT std_ulogic_vector(3 DOWNTO 0);
sign_o : OUT std_ulogic);
END COMPONENT;
SIGNAL a : signed(3 DOWNTO 0);
SIGNAL b : signed(3 DOWNTO 0);
SIGNAL sum : signed(3 DOWNTO 0);
SIGNAL sum_sm : std_ulogic_vector(3 DOWNTO 0);
BEGIN
-- connecting switches to operands
a <= unsigned(SW(3 DOWNTO 0));
b <= unsigned(SW(7 DOWNTO 4));
a <= signed(SW(3 DOWNTO 0));
b <= signed(SW(7 DOWNTO 4));
-- add the operands
sum <= resize(a, sum'length) + resize(b, sum'length);
......@@ -47,10 +55,17 @@ BEGIN
LEDR(7 DOWNTO 4) <= SW(7 DOWNTO 4);
-- LEDR(7) <= '0';
-- convert 2'sc to sign-magnitude
signmag_sum : twosc2sm
PORT MAP (
value_sc_i => std_ulogic_vector(sum),
value_sm_o => sum_sm,
sign_o => LEDR(8));
-- display result on HEX0
result_sum : binto7segment
PORT MAP (
bin_i => std_ulogic_vector(sum),
bin_i => sum_sm,
segments_o => HEX0);
END structure;
......
-------------------------------------------------------------------------------
-- Module : twosc2sm
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY twosc2sm IS
PORT (value_sc_i : IN std_ulogic_vector(3 DOWNTO 0);
value_sm_o : OUT std_ulogic_vector(3 DOWNTO 0);
sign_o : OUT std_ulogic
);
END twosc2sm;
ARCHITECTURE rtl OF twosc2sm IS
SIGNAL value_3bit : unsigned(2 DOWNTO 0);
SIGNAL value_4bit : unsigned(3 DOWNTO 0);
BEGIN
sign_output : sign_o <= value_sc_i(3);
value_3bit_signal : value_3bit <= unsigned(value_sc_i(2 DOWNTO 0));
value_4bit_signal : value_4bit <= resize(value_3bit, value_sm_o'length);
value_sm_output: value_sm_o <= std_ulogic_vector(value_4bit);
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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