lab#8 tone_rtl modified

sim/de1_tone/de1_tone.cr.mti

+

sim/de1_tone/modelsim_sources.tcl

+project addfile ../../src/adcintf.vhd
+project addfile ../../src/bclk.vhd
+project addfile ../../src/dacintf.vhd
+project addfile ../../src/fsgen.vhd
+project addfile ../../src/i2c_sub.vhd
+project addfile ../../src/i2c.vhd
+project addfile ../../src/i2c_write.vhd
+project addfile ../../src/mclk.vhd
+project addfile ../../src/audio.vhd
+project addfile ../../src/tone_rtl.vhd
+project addfile ../../src/de1_tone.vhd
+project addfile ../../src/t_de1_tone.vhd

sim/de1_tone/transcript

+# project open de1_tone 
+# Loading project de1_tone
+#  vsim work.t_de1_tone(tbench) 
+# vsim work.t_de1_tone(tbench) 
+# Loading std.standard
+# Loading std.textio(body)
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading ieee.math_real(body)
+# Loading work.t_de1_tone(tbench)
+# Loading ieee.vital_timing(body)
+# Loading ieee.vital_primitives(body)
+# Loading altera.dffeas_pack
+# Loading altera.altera_primitives_components
+# Loading work.de1_tone(struct)
+# Loading work.audio(struct)
+# Loading work.i2c_sub(struct)
+# Loading work.i2c(rtl)
+# Loading work.i2c_write(rtl)
+# Loading work.mclk(rtl)
+# Loading work.bclk(rtl)
+# Loading work.fsgen(rtl)
+# Loading work.dacintf(rtl)
+# Loading work.adcintf(rtl)
+# Loading work.tone(rtl)
+# Loading altera.opndrn(behavior)
+#  add wave * 
+#  run -a 
+# ** Warning: NUMERIC_STD.TO_SIGNED: vector truncated
+#    Time: 0 ns  Iteration: 0  Instance: /t_de1_tone
+#  

src/tone_rtl.vhd

@@ -10,10 +10,40 @@ entity tone is
         audio_o    : out std_ulogic_vector(15 downto 0));
 end entity;
 
-architecture rtl of tone is
+architecture rtl of tone IS
+
+  SIGNAL incrementer     : std_ulogic;
+  SIGNAL count_o         : unsigned(13 DOWNTO 0);
+  SIGNAL count_i         : unsigned(13 DOWNTO 0);
+  SIGNAL count_rst       : std_ulogic;
+
+  SIGNAL current_state   : signed(15 DOWNTO 0);
+  SIGNAL next_state      : signed(15 DOWNTO 0);
+  
   
 begin
 
-audio_o <= audio_i when rising_edge(clk) and dv_i = '1';
+  -- audio_o <= audio_i when rising_edge(clk) and dv_i = '1';
+
+  -- phase counter
+  count_ouput : count_o <= count_i + 1 WHEN count_rst = '0' ELSE to_unsigned(0, count_o'length);
+
+  count_input : count_i <= to_unsigned(0, current_state'length) WHEN rst_n = '0' ELSE
+                           count_o WHEN rising_edge(clk);
+
+  count_reset : count_rst <= '1' WHEN count_o = to_unsigned(8332, count_o'length) ELSE '0';
+
+  incrementer_signal : incrementer <= '1' WHEN count_o <= to_unsigned(2083, count_o'length) AND count_o > to_unsigned(6249, count_o'length) ELSE '0';
+
+
+  -- output counter
+  state_register : current_state <= to_signed(0, current_state'length) WHEN rst_n = '0' ELSE
+                                    next_state WHEN rising_edge(clk);
+
+  next_state_output : next_state <= current_state + 0.00048007681 WHEN incrementer = '0' ELSE
+                                    current_state - 0.00048007681;
+
+  audio_output : audio_o <= std_ulogic_vector(current_state);
+
 
 end architecture rtl;