lab#4_de1_cntupen_step

src/de1_cntupen_step_structure.vhd

@@ -64,12 +64,12 @@ BEGIN
   long_pulse <= KEY(1);
 
 
-  DUT : ENTITY work.falling_edge_detector(rtl)
+  single_pulse_generator : ENTITY work.falling_edge_detector(rtl)
     PORT MAP (
       x_i     => long_pulse,
       clk_i   => clk_i,
       rst_ni  => rst_ni,
-      rise_o  => en_pi
+      fall_o  => en_pi
       );
   
   -- connecting device under test with peripheral elements
@@ -77,15 +77,17 @@ BEGIN
     PORT MAP (
       clk_i   => clk_i,
       rst_ni  => rst_ni,
-      en_pi   => rise_o,
+      en_pi   => en_pi,
       count_o => count_o
       );
+  
   -- connecting count value to HEX display
   count_value : ENTITY work.binto7segment(truthtable)
     PORT MAP (
       bin_i => count_o,
       segments_o => HEX0       
-      );  
+      );
+  
 END structure;
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 -- Revisions: