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Oran Garrity
vlsilab21_garrity_mikschl
Commits
12a1a407
Commit
12a1a407
authored
Mar 30, 2021
by
Manuel Mikschl
Browse files
lab#4_de1_cntupen_step
parent
9dc566c0
Changes
1
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src/de1_cntupen_step_structure.vhd
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12a1a407
...
...
@@ -64,12 +64,12 @@ BEGIN
long_pulse
<=
KEY
(
1
);
DUT
:
ENTITY
work
.
falling_edge_detector
(
rtl
)
single_pulse_generator
:
ENTITY
work
.
falling_edge_detector
(
rtl
)
PORT
MAP
(
x_i
=>
long_pulse
,
clk_i
=>
clk_i
,
rst_ni
=>
rst_ni
,
rise
_o
=>
en_pi
fall
_o
=>
en_pi
);
-- connecting device under test with peripheral elements
...
...
@@ -77,15 +77,17 @@ BEGIN
PORT
MAP
(
clk_i
=>
clk_i
,
rst_ni
=>
rst_ni
,
en_pi
=>
rise_o
,
en_pi
=>
en_pi
,
count_o
=>
count_o
);
-- connecting count value to HEX display
count_value
:
ENTITY
work
.
binto7segment
(
truthtable
)
PORT
MAP
(
bin_i
=>
count_o
,
segments_o
=>
HEX0
);
);
END
structure
;
-------------------------------------------------------------------------------
-- Revisions:
...
...
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