Commit 12a1a407 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab#4_de1_cntupen_step

parent 9dc566c0
...@@ -64,12 +64,12 @@ BEGIN ...@@ -64,12 +64,12 @@ BEGIN
long_pulse <= KEY(1); long_pulse <= KEY(1);
DUT : ENTITY work.falling_edge_detector(rtl) single_pulse_generator : ENTITY work.falling_edge_detector(rtl)
PORT MAP ( PORT MAP (
x_i => long_pulse, x_i => long_pulse,
clk_i => clk_i, clk_i => clk_i,
rst_ni => rst_ni, rst_ni => rst_ni,
rise_o => en_pi fall_o => en_pi
); );
-- connecting device under test with peripheral elements -- connecting device under test with peripheral elements
...@@ -77,15 +77,17 @@ BEGIN ...@@ -77,15 +77,17 @@ BEGIN
PORT MAP ( PORT MAP (
clk_i => clk_i, clk_i => clk_i,
rst_ni => rst_ni, rst_ni => rst_ni,
en_pi => rise_o, en_pi => en_pi,
count_o => count_o count_o => count_o
); );
-- connecting count value to HEX display -- connecting count value to HEX display
count_value : ENTITY work.binto7segment(truthtable) count_value : ENTITY work.binto7segment(truthtable)
PORT MAP ( PORT MAP (
bin_i => count_o, bin_i => count_o,
segments_o => HEX0 segments_o => HEX0
); );
END structure; END structure;
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions: -- Revisions:
......
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