LAB#10 Audio Game

src/de1_play_structure.vhd

@@ -10,6 +10,7 @@ entity de1_play is
     KEY         : in    std_ulogic_vector(1 downto 0);
     I2C_SCLK    : out   std_ulogic;
     I2C_SDAT    : inout std_logic;
+    SW_i        : in    std_ulogic_vector(9 downto 0);
     AUD_ADCLRCK : out   std_ulogic;
     AUD_ADCDAT  : in    std_ulogic;
     AUD_DACLRCK : out   std_ulogic;
@@ -69,12 +70,15 @@ architecture structure of de1_play is
   component play is
   port (clk        : in  std_ulogic;
         rst_n      : in  std_ulogic;
+        tone_o     : OUT std_ulogic;
         onesec_i   : in  std_ulogic;
         key_i      : in  std_ulogic;
         led_o      : out std_ulogic_vector(4 downto 0));
   end component;
 
   signal clk      : std_ulogic;
+  signal audio_o  : std_ulogic_vector(15 downto 0);
+  SIGNAL tone_o   : std_ulogic;
   signal rst_n    : std_ulogic;
   signal key_inv  : std_ulogic;
   signal key_edge : std_ulogic;
@@ -115,6 +119,7 @@ begin
   play_i0 : play
     port map (
       clk      => clk,
+      tone_o   => tone_o,
       rst_n    => rst_n,
       onesec_i => one_second_period,
       key_i    => key_edge,
@@ -144,8 +149,11 @@ begin
       rst_n      => rst_n,
       dv_i       => adc_valid,
       audio_i    => adc_data,
-      audio_o    => dac_data,
-      switches_i => "0000000000");
+      audio_o    => audio_o,
+      switches_i => SW_i);
+
+  -- select if tone is activated or not
+  dac_data <= audio_o WHEN tone_o = '1' ELSE "0000000000000000";
 
     -- i2c has an open-drain ouput
   i2c_dat_i <= I2C_SDAT;

src/play_rtl.vhd

@@ -34,6 +34,7 @@ use ieee.std_logic_1164.all;
 entity play is
   port (clk        : in  std_ulogic;
         rst_n      : in  std_ulogic;
+        tone_o     : OUT std_ulogic;
         onesec_i   : in  std_ulogic;
         key_i      : in  std_ulogic;
         led_o      : out std_ulogic_vector(4 downto 0));
@@ -43,7 +44,6 @@ architecture rtl of play is
 
   type state_t is (start_s,one_s,chance_s,four_s,last_s,hit0_s,hit1_s);
   signal current_state,next_state : state_t;
-  signal key_press : std_ulogic;
 
 begin
 
@@ -51,8 +51,11 @@ begin
 
   next_p : process(current_state, onesec_i, key_i)
     begin
+
       next_state <= current_state;
       led_o <= "00000";
+      tone_o <= '0';
+      
       case current_state is
         when start_s =>
           led_o <= "10000";
@@ -67,12 +70,8 @@ begin
         when chance_s =>
           led_o <= "00100";
           if key_i = '1' then
-			   key_press <= '1';
-			 end if;
-			 if key_press = '1' AND onesec_i = '1' then 
-				key_press <= '0';
-				next_state <= hit0_s;
-			 elsif onesec_i = '1' then
+            next_state <= hit0_s;
+          elsif onesec_i = '1' then
             next_state <= four_s; 
           end if;
         when four_s =>
@@ -87,26 +86,20 @@ begin
           end if;
         when hit0_s =>
           led_o <= "10000";
-          if key_i = '1' then
-					key_press <= '1';
-			end if;
-            if onesec_i = '1' AND key_press = '1' then
-				  key_press <= '0';
-				  next_state <= chance_s;
+          if key_i = '1' THEN
+            next_state <= chance_s;
           elsif onesec_i = '1' then
             next_state <= hit1_s;
           end if;
         when hit1_s =>
           led_o <= "00001";
-          if key_i = '1' then
-				key_press <= '1';
-			end if;
-            if onesec_i = '1' AND key_press = '1' then
-				  key_press <= '0';
-				  next_state <= chance_s;
-          elsif onesec_i = '1' then
-            next_state <= hit0_s;
-          end if;         
+          tone_o <='1';
+        if key_i = '1' then
+          next_state <= chance_s;
+        elsif onesec_i = '1' then
+         next_state <= hit0_s;
+        end if;
+          
         when others => null;
       end case;
     end process;