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Oran Garrity
vlsilab21_garrity_mikschl
Commits
180a9608
Commit
180a9608
authored
Apr 20, 2021
by
Friedrich Beckmann
Committed by
Manuel Mikschl
Apr 20, 2021
Browse files
added demo project for static timing analysis
parent
53d3c501
Changes
3
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pnr/de1_sta/de1_sta_pins.tcl
0 → 100644
View file @
180a9608
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW
[
0
]
set_location_assignment PIN_L21 -to SW
[
1
]
set_location_assignment PIN_M22 -to SW
[
2
]
set_location_assignment PIN_V12 -to SW
[
3
]
set_location_assignment PIN_W12 -to SW
[
4
]
set_location_assignment PIN_U12 -to SW
[
5
]
set_location_assignment PIN_U11 -to SW
[
6
]
set_location_assignment PIN_M2 -to SW
[
7
]
set_location_assignment PIN_M1 -to SW
[
8
]
set_location_assignment PIN_R20 -to LEDR
[
0
]
set_location_assignment PIN_R19 -to LEDR
[
1
]
set_location_assignment PIN_U19 -to LEDR
[
2
]
set_location_assignment PIN_Y19 -to LEDR
[
3
]
set_location_assignment PIN_T18 -to LEDR
[
4
]
set_location_assignment PIN_V19 -to LEDR
[
5
]
set_location_assignment PIN_Y18 -to LEDR
[
6
]
set_location_assignment PIN_U18 -to LEDR
[
7
]
set_location_assignment PIN_R18 -to LEDR
[
8
]
set_location_assignment PIN_U22 -to LEDG
[
0
]
set_location_assignment PIN_U21 -to LEDG
[
1
]
set_location_assignment PIN_V22 -to LEDG
[
2
]
set_location_assignment PIN_V21 -to LEDG
[
3
]
set_location_assignment PIN_W22 -to LEDG
[
4
]
set_location_assignment PIN_J2 -to HEX0
[
0
]
set_location_assignment PIN_J1 -to HEX0
[
1
]
set_location_assignment PIN_H2 -to HEX0
[
2
]
set_location_assignment PIN_H1 -to HEX0
[
3
]
set_location_assignment PIN_F2 -to HEX0
[
4
]
set_location_assignment PIN_F1 -to HEX0
[
5
]
set_location_assignment PIN_E2 -to HEX0
[
6
]
set_location_assignment PIN_E1 -to HEX1
[
0
]
set_location_assignment PIN_H6 -to HEX1
[
1
]
set_location_assignment PIN_H5 -to HEX1
[
2
]
set_location_assignment PIN_H4 -to HEX1
[
3
]
set_location_assignment PIN_G3 -to HEX1
[
4
]
set_location_assignment PIN_D2 -to HEX1
[
5
]
set_location_assignment PIN_D1 -to HEX1
[
6
]
set_location_assignment PIN_G5 -to HEX2
[
0
]
set_location_assignment PIN_G6 -to HEX2
[
1
]
set_location_assignment PIN_C2 -to HEX2
[
2
]
set_location_assignment PIN_C1 -to HEX2
[
3
]
set_location_assignment PIN_E3 -to HEX2
[
4
]
set_location_assignment PIN_E4 -to HEX2
[
5
]
set_location_assignment PIN_D3 -to HEX2
[
6
]
set_location_assignment PIN_H12 -to GPO_1
[
0
]
set_location_assignment PIN_H13 -to GPO_1
[
1
]
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_H14 -to GPI_1_2
# ----------------------------------------------------------------------------
pnr/de1_sta/makefile
0 → 100644
View file @
180a9608
PROJECT
=
de1_sta
# Prototype Board FPGA family and device settings
# DE1
FAMILY
=
"Cyclone II"
DEVICE
=
EP2C20F484C7
PROGFILEEXT
=
sof
SOURCE_FILES
=
\
../../src/de1_sta.vhd
include
../makefile
src/de1_sta.vhd
0 → 100644
View file @
180a9608
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
de1_sta
is
port
(
CLOCK_50
:
in
std_ulogic
;
x_i
:
in
unsigned
(
7
downto
0
);
y_o
:
out
unsigned
(
x_i
'range
)
);
end
de1_sta
;
architecture
rtl
of
de1_sta
is
signal
a
,
b
,
c
,
d
:
unsigned
(
x_i
'range
);
signal
sum
:
unsigned
(
x_i
'range
);
signal
clk
:
std_ulogic
;
begin
clk
<=
CLOCK_50
;
sum
<=
a
+
b
+
c
+
d
;
y_o
<=
sum
when
rising_edge
(
clk
);
a
<=
x_i
when
rising_edge
(
clk
);
b
<=
a
when
rising_edge
(
clk
);
c
<=
b
when
rising_edge
(
clk
);
d
<=
c
when
rising_edge
(
clk
);
end
architecture
;
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