LAB#10 Tone

src/t_de1_tone.vhd

@@ -40,7 +40,7 @@ architecture tbench of t_de1_tone is
       );
   end component;
 
-  COMPONENT tone_rtl IS
+  COMPONENT tone IS
     port(
       clk         : IN  std_ulogic;
       rst_n       : IN  std_ulogic;
@@ -91,12 +91,12 @@ begin
       
   
   -- test tone generator for triangular signal
-  MUV : tone_rtl
+  MUV : tone
     PORT MAP (
       clk        => clk,
       rst_n      => reset_n,
-      switches_i => "0000000000",
-      dv_i       => '1', 
+      switches_i => switches,
+      dv_i       => dv_i, 
       audio_i    => "0000000000000000",
       audio_o    => audio_triangular
       ); 
@@ -112,6 +112,17 @@ begin
       wait;
     end if;
   end process clock_p;
+  
+  dv_input : process
+  begin
+    dv_i <= '0';
+    wait for 21 us;
+    dv_i <= '1';
+    wait for 20 ns;
+    if not simrun then
+      wait;
+    end if;
+  end process dv_input;
 
   simrun <= false after 5 ms;
 
@@ -122,6 +133,15 @@ begin
     reset_n <= '1';
     wait;
   end process reset_p;
+  
+  switches_p : process
+  begin
+    switches <= "0000000001";
+    wait for 3 ms;
+    switches <= "0000001000";
+    wait;
+  end process switches_p;
+
 
   aud_adcdat <= test_tone_quantized(bit_count mod 16);
 

src/tone_rtl.vhd

@@ -12,9 +12,24 @@ entity tone is
 end entity;
 
 architecture rtl of tone IS
-SIGNAL phase_increment : std
+  SIGNAL phase           : unsigned(15 DOWNTO 0);
+  SIGNAL phase_increment : unsigned(15 DOWNTO 0);
+  SIGNAL tone            : signed(31 DOWNTO 0);
+  SIGNAL switches        : unsigned(15 DOWNTO 0);
+  
+  constant phase_const   : unsigned(15 DOWNTO 0) := to_unsigned((2**16)/48,16);
   
 begin
+  
+  switches <= resize(unsigned(switches_i(9 DOWNTO 0)),16);
+  
+  audio_o <= std_ulogic_vector(resize(tone,audio_o'length)) WHEN rising_edge(clk) AND dv_i = '1';
 
-
+  phase_increment <= resize((switches*phase_const),phase_increment'length);
+  
+  phase <= (OTHERS => '0') WHEN rst_n = '0' ELSE
+           phase + phase_increment WHEN rising_edge(clk) AND dv_i = '1';
+  
+  tone <= resize(31/16*(abs(signed(resize(phase,tone'length))-2**15)-2**14),tone'length); 
+             
 end architecture rtl;