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Oran Garrity
vlsilab21_garrity_mikschl
Commits
1c425e57
Commit
1c425e57
authored
Apr 22, 2021
by
Manuel Mikschl
Browse files
lab#7: heartbeat_gen protoype testing
parent
742661e1
Changes
2
Hide whitespace changes
Inline
Side-by-side
pnr/de1_heartbeat_gen/makefile
View file @
1c425e57
...
...
@@ -46,7 +46,8 @@ include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES
=
$(SYN_SOURCE_FILES)
\
../../src/
$(PROJECT)
_rtl.vhd
../../src/
$(PROJECT)
_structure.vhd
\
../../src/cntdnmodm_rtl.vhd
include
../makefile
...
...
src/de1_heartbeat_gen_structure.vhd
View file @
1c425e57
...
...
@@ -11,9 +11,9 @@ USE IEEE.numeric_std.ALL;
ENTITY
de1_heartbeat_gen
IS
PORT
(
CLOCK_50
:
IN
std_ulogic
;
CLOCK_50
:
IN
std_ulogic
;
KEY0
:
IN
std_ulogic
;
LEDR
:
OUT
std_ulogic_vector
(
9
DOWNTO
0
)
;
LEDR
:
OUT
std_ulogic_vector
(
9
DOWNTO
0
)
);
END
de1_heartbeat_gen
;
...
...
@@ -24,7 +24,9 @@ ARCHITECTURE structure OF de1_heartbeat_gen IS
clk_i
:
IN
std_ulogic
;
rst_ni
:
IN
std_ulogic
;
en_pi
:
IN
std_ulogic
;
count_o
:
OUT
std_ulogic_vector
(
9
DOWNTO
0
));
tc_o
:
OUT
std_ulogic
;
count_o
:
OUT
std_ulogic_vector
(
9
DOWNTO
0
)
);
END
COMPONENT
cntdnmodm
;
COMPONENT
heartbeat_gen
IS
...
...
@@ -33,16 +35,35 @@ ARCHITECTURE structure OF de1_heartbeat_gen IS
rst_ni
:
IN
std_ulogic
;
en_pi
:
IN
std_ulogic
;
cout_o
:
OUT
std_ulogic_vector
(
9
DOWNTO
0
);
heartbeat_o
:
OUT
std_ulogic
);
heartbeat_o
:
OUT
std_ulogic
);
END
COMPONENT
heartbeat_gen
;
SIGNAL
SIGNAL
clk_i
:
std_ulogic
;
SIGNAL
rst_ni
:
std_ulogic
;
SIGNAL
en_pi
:
std_ulogic
;
SIGNAL
count_o
:
std_ulogic_vector
(
9
DOWNTO
0
);
SIGNAL
tc_o
:
std_ulogic
;
SIGNAL
heartbeat_o
:
std_ulogic
;
BEGIN
-- connectiong signals to keys etc.
clk_i
<=
CLOCK_50
;
rst_ni
<=
KEY0
;
LEDR
(
0
)
<=
heartbeat_o
;
LEDR
(
1
)
<=
heartbeat_o
;
LEDR
(
2
)
<=
heartbeat_o
;
LEDR
(
3
)
<=
heartbeat_o
;
LEDR
(
4
)
<=
heartbeat_o
;
LEDR
(
5
)
<=
heartbeat_o
;
LEDR
(
6
)
<=
heartbeat_o
;
LEDR
(
7
)
<=
heartbeat_o
;
LEDR
(
8
)
<=
heartbeat_o
;
LEDR
(
9
)
<=
heartbeat_o
;
-- connecting prescaler with peripheral elements and heartbeat generator
prescaler
:
ENTITY
work
.
cntdnmodm
...
...
@@ -50,21 +71,24 @@ BEGIN
n
=>
16
,
m
=>
50000
)
PORT
MAP
(
clk_i
=>
rst_ni
=>
en_pi
=>
count_o
=>
tc_o
=>
);
clk_i
=>
clk_i
,
rst_ni
=>
rst_ni
,
en_pi
=>
'1'
,
count_o
=>
OPEN
,
tc_o
=>
tc_o
);
-- connecting heartbeat generator with peripheral elements and prescaler
heartbeat_generator
:
ENTITY
work
.
heartbeat_gen
PORT
MAP
(
clk_i
=>
rst_ni
=>
en_pi
=>
count_o
=>
heartbeat_o
=>
);
clk_i
=>
clk_i
,
rst_ni
=>
rst_ni
,
en_pi
=>
tc_o
,
count_o
=>
OPEN
,
heartbeat_o
=>
heartbeat_o
);
END
structure
;
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