Commit 1d9fa5b5 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

bugfix in lfsr_18bit and sequence_detector_18bit

parent fc212f2b
......@@ -13,7 +13,7 @@
SYN_SOURCE_FILES = \
../../src/sequence_detector_18bit.vhd \
../../src/lfsr_18bit.vhd \
../../src/cntupen_rtl.vhd
../../src/cntupen_16bit_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
project addfile ../../src/sequence_detector_18bit.vhd
project addfile ../../src/lfsr_18bit.vhd
project addfile ../../src/cntupen_16bit_rtl.vhd
project addfile ../../src/t_sequence_detector_18bit.vhd
;; ----------------------------------------------------------------------------
;; Script : modelsim.ini
;; ----------------------------------------------------------------------------
;; Author : Johann Faerber
;; Company : University of Applied Sciences Augsburg
;; ----------------------------------------------------------------------------
;; Description: original version modified
;; - deleted all VHDL and Verilog device libraries
;; - modified compiler standard to VHDL93 = 2008
;; ----------------------------------------------------------------------------
;; Revisions : see end of file
;; ----------------------------------------------------------------------------
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; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
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; in that order, and no other conversion codes. The %s represents
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; GenerateFormat = %s__%d
; Specify whether checkpoint files should be compressed.
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; or more of: -force -nobreakpoint -nolist -nolog -nowave
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; simulation ends. A value of 1 will cause the WLF file to be deleted.
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; Automatic SDF compilation
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[lmc]
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; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
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; msgmode = both
;; ----------------------------------------------------------------------------
;; Revisions:
;; ----------
;; $Id:$
;; ----------------------------------------------------------------------------
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 4
Project_File_0 = /home/caeuser/Projects/VLSI/vlsilab21_garrity_mikschl/src/cntupen_16bit_rtl.vhd
Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1625491371 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2008
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Project_File_2 = /home/caeuser/Projects/VLSI/vlsilab21_garrity_mikschl/src/sequence_detector_18bit.vhd
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Project_Major_Version = 10
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# project open sequence_detector_18bit
# Loading project sequence_detector_18bit
# vsim work.t_sequence_detector_18bit(tbench)
# vsim work.t_sequence_detector_18bit(tbench)
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.t_sequence_detector_18bit(tbench)
# Loading work.sequence_detector_18bit(behave)
# Loading ieee.numeric_std(body)
# Loading work.lfsr_18bit(rtl)
# Loading work.cntupen_16bit(rtl)
# add wave *
# run -a
# ** Warning: NUMERIC_STD."=": metavalue detected, returning FALSE
# Time: 0 ns Iteration: 0 Instance: /t_sequence_detector_18bit/LFSR
#
# Current time Mon Jul 5 15:17:08 2021
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1d"
# Version = "2012.11"
# Date = "Nov 2 2012"
# Platform = linuxpe
# 0 0xf7fd3069: '<unknown (@0xf7fd3069)>'
# End of Stack Trace
# Current time Mon Jul 5 15:17:08 2021
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1d"
# Version = "2012.11"
# Date = "Nov 2 2012"
# Platform = linuxpe
# 0 0xf7fd3069: '<unknown (@0xf7fd3069)>'
# End of Stack Trace
-------------------------------------------------------------------------------
-- 16 bit up counter with enable
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY cntupen_16bit IS
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector(15 DOWNTO 0)
);
END cntupen_16bit;
ARCHITECTURE rtl OF cntupen_16bit IS
-- datatype unsigned is defined in package numeric_std
SIGNAL next_state, current_state : unsigned(15 DOWNTO 0);
BEGIN
-- package numeric_std overloads operator '+'
-- for arguments of different types, here: unsigned and integer
incrementer : next_state <= current_state + 1;
-- synthesisable construct of a d-type register with synchronrous enable
state_register : current_state <= "1111111111111111" WHEN rst_ni = '0' ELSE
next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
-- type conversion from unsignd to std_ulogic_vector necessary
counter_output : count_o <= std_ulogic_vector(current_state);
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
......@@ -8,7 +8,7 @@ LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lfsr_fibonacci IS
ENTITY lfsr_18bit IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
......@@ -17,9 +17,9 @@ ENTITY lfsr_fibonacci IS
noise_o : OUT std_ulogic;
eoc_po : OUT std_ulogic
);
END lfsr_fibonacci;
END lfsr_18bit;
ARCHITECTURE rtl OF lfsr_fibonacci IS
ARCHITECTURE rtl OF lfsr_18bit IS
SIGNAL q : std_ulogic_vector(17 DOWNTO 0);
SIGNAL d : std_ulogic_vector(17 DOWNTO 0);
......@@ -43,24 +43,8 @@ BEGIN
eoc_po <= period_output WHEN rising_edge(clk_i);
-- next state logic
d(0) <= q(1);
d(1) <= q(2);
d(2) <= q(3);
d(3) <= q(4);
d(4) <= q(5);
d(5) <= q(6);
d(6) <= q(7);
d(7) <= q(8);
d(8) <= q(9);
d(9) <= q(10);
d(10) <= q(11);
d(11) <= q(12);
d(12) <= q(13);
d(13) <= q(14);
d(14) <= q(15);
d(15) <= q(16);
d(16) <= q(17);
d(17) <= q(6) XOR q(0);
d(16 downto 0) <= q(17 downto 1);
d(17) <= q(7) XOR q(0);
-- current state
......
......@@ -18,14 +18,14 @@ LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY sequence_detector_0010001 IS
ENTITY sequence_detector_18bit IS
PORT (clk: IN std_ulogic;
rst_n: IN std_ulogic;
ser_i: IN std_ulogic;
done_o: OUT std_ulogic);
END sequence_detector_0010001;
END sequence_detector_18bit;
ARCHITECTURE behave OF sequence_detector_0010001 IS
ARCHITECTURE behave OF sequence_detector_18bit IS
TYPE state_type IS (State_0, State_1, State_2, State_3, State_4, State_5, State_6, State_7);
SIGNAL next_state, current_state : state_type;
......
......@@ -16,13 +16,13 @@ USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_sequence_detector_18bit IS
END ENTITY t_sequence_detector_18bit;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_sequence_detector_18bit IS
-- component sequence detector (18 bit)
COMPONENT sequence_detector_18bit IS
PORT (
clk : IN std_ulogic;
......@@ -31,6 +31,7 @@ ARCHITECTURE tbench OF t_sequence_detector_18bit IS
done_o : OUT std_ulogic);
END COMPONENT sequence_detector_18bit;
-- component lfsr (18 bit)
COMPONENT lfsr_18bit IS
PORT (
clk_i : IN std_ulogic;
......@@ -40,8 +41,17 @@ ARCHITECTURE tbench OF t_sequence_detector_18bit IS
noise_o : OUT std_ulogic;
eoc_po : OUT std_ulogic);
END COMPONENT lfsr_18bit;
-- component up counter (16 bit)
COMPONENT cntupen_16bit IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector(15 DOWNTO 0));
END COMPONENT cntupen_16bit;
-- component ports
SIGNAL clk_i : std_ulogic;
SIGNAL rst_ni : std_ulogic;
......@@ -51,6 +61,9 @@ ARCHITECTURE tbench OF t_sequence_detector_18bit IS
SIGNAL en_pi : std_ulogic;
SIGNAL lfsr_o : std_ulogic_vector(17 DOWNTO 0);