Commit 259838f0 authored by Oran Garrity's avatar Oran Garrity
Browse files

LAB#10 Tone fix in progress

parent 12e3f34d
......@@ -12,45 +12,9 @@ entity tone is
end entity;
architecture rtl of tone IS
SIGNAL incrementer : std_ulogic;
SIGNAL count_o : unsigned(14 DOWNTO 0);
SIGNAL count_i : unsigned(14 DOWNTO 0);
SIGNAL count_rst : std_ulogic;
SIGNAL current_state : signed(15 DOWNTO 0);
SIGNAL next_state : signed(15 DOWNTO 0);
SIGNAL phase_increment : std
begin
-- audio_o <= audio_i when rising_edge(clk) and dv_i = '1';
-- phase counter
count_ouput : count_o <= count_i + 1 WHEN count_rst = '0' ELSE to_unsigned(0, count_o'length);
count_input : count_i <= to_unsigned(0, count_i'length) WHEN rst_n = '0' OR count_rst = '1' ELSE
count_o WHEN rising_edge(clk);
count_reset : count_rst <= '1' WHEN count_o = to_unsigned(8332, count_o'length) ELSE '0';
incrementer_signal : incrementer <= '1' WHEN count_o <= to_unsigned(2083, count_o'length) OR count_o > to_unsigned(6249, count_o'length) ELSE '0';
-- output counter
state_register : current_state <= to_signed(0, current_state'length) WHEN rst_n = '0' ELSE
next_state WHEN rising_edge(clk);
next_state_output : next_state <= current_state + 1 WHEN incrementer = '1' ELSE
current_state - 1;
-- 0.00048007681
audio_output : audio_o <= std_ulogic_vector(current_state);
end architecture rtl;
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