Commit 35f21e22 authored by Oran Garrity's avatar Oran Garrity
Browse files

Lab#9 18 bit

parent 5d288979
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# assign variable PROJECT with the top level project name
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = sequence_detector_18bit
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/sequence_detector_18bit.vhd \
../../src/lfsr_18bit.vhd \
../../src/cntupen_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : lfsr_18bit
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lfsr_fibonacci IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
lfsr_o : OUT std_ulogic_vector(17 DOWNTO 0);
noise_o : OUT std_ulogic;
eoc_po : OUT std_ulogic
);
END lfsr_fibonacci;
ARCHITECTURE rtl OF lfsr_fibonacci IS
SIGNAL q : std_ulogic_vector(17 DOWNTO 0);
SIGNAL d : std_ulogic_vector(17 DOWNTO 0);
SIGNAL count_next_state : unsigned(17 DOWNTO 0);
SIGNAL count_current_state : unsigned(17 DOWNTO 0);
SIGNAL period_output : std_ulogic;
BEGIN
-- counter for eoc_po
count_next_state <= count_current_state + 1 WHEN eoc_po = '0' ELSE
count_current_state + 2;
count_current_state <= to_unsigned(0, count_current_state'length) WHEN rst_ni = '0' ELSE
count_next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
period_output <= '1' WHEN count_current_state = to_unsigned(262143, count_current_state'length) ELSE '0';
eoc_po <= period_output WHEN rising_edge(clk_i);
-- next state logic
d(0) <= q(1);
d(1) <= q(2);
d(2) <= q(3);
d(3) <= q(4);
d(4) <= q(5);
d(5) <= q(6);
d(6) <= q(7);
d(7) <= q(8);
d(8) <= q(9);
d(9) <= q(10);
d(10) <= q(11);
d(11) <= q(12);
d(12) <= q(13);
d(13) <= q(14);
d(14) <= q(15);
d(15) <= q(16);
d(16) <= q(17);
d(17) <= q(6) XOR q(0);
-- current state
q <= "000000000000000001" WHEN rst_ni = '0' ELSE
d WHEN rising_edge(clk_i);
-- noise output
noise_o <= q(0);
-- parrallel output
lfsr_o <= q;
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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-- This file was generated by
-- Qfsm Version 0.55
-- (C) Stefan Duffner, Rainer Strobel, Aaron Erhardt
-- Inputs: ser_i
-- State/Output done_o
-- State_0 0
-- State_1 0
-- State_2 0
-- State_3 0
-- State_4 0
-- State_5 0
-- State_6 0
-- State_7 1
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY sequence_detector_0010001 IS
PORT (clk: IN std_ulogic;
rst_n: IN std_ulogic;
ser_i: IN std_ulogic;
done_o: OUT std_ulogic);
END sequence_detector_0010001;
ARCHITECTURE behave OF sequence_detector_0010001 IS
TYPE state_type IS (State_0, State_1, State_2, State_3, State_4, State_5, State_6, State_7);
SIGNAL next_state, current_state : state_type;
BEGIN
state_register: PROCESS (rst_n, clk)
BEGIN
IF rst_n='0' THEN
current_state <= State_0;
ELSIF rising_edge(clk) THEN
current_state <= next_state;
END IF;
END PROCESS;
next_state_and_output_logic: PROCESS (current_state, ser_i)
VARIABLE temp_input : std_ulogic_vector(0 DOWNTO 0);
VARIABLE temp_output : std_ulogic_vector(0 DOWNTO 0);
BEGIN
temp_input(0) := ser_i;
CASE current_state IS
WHEN State_0 => temp_output := "0";
IF temp_input="0" THEN
next_state <= State_1;
ELSIF temp_input="1" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_1 => temp_output := "0";
IF temp_input="0" THEN
next_state <= State_2;
ELSIF temp_input="1" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_2 => temp_output := "0";
IF temp_input="1" THEN
next_state <= State_3;
ELSIF temp_input="0" THEN
next_state <= State_1;
ELSE
next_state <= current_state;
END IF;
WHEN State_3 => temp_output := "0";
IF temp_input="0" THEN
next_state <= State_4;
ELSIF temp_input="1" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_4 => temp_output := "0";
IF temp_input="0" THEN
next_state <= State_5;
ELSIF temp_input="1" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_5 => temp_output := "0";
IF temp_input="0" THEN
next_state <= State_6;
ELSIF temp_input="1" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_6 => temp_output := "0";
IF temp_input="1" THEN
next_state <= State_7;
ELSIF temp_input="0" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_7 => temp_output := "1";
IF temp_input="0" THEN
next_state <= State_1;
ELSIF temp_input="1" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN OTHERS => temp_output := (OTHERS =>'X');
next_state <= State_0;
END CASE;
done_o <= temp_output(0);
END PROCESS;
END behave;
-------------------------------------------------------------------------------
-- Module :
-------------------------------------------------------------------------------
-- Author : <johann.faerber@hs-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2021 <johann.faerber@hs-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "sequence_detector"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_sequence_detector_18bit IS
END ENTITY t_sequence_detector_18bit;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_sequence_detector_18bit IS
COMPONENT sequence_detector_18bit IS
PORT (
clk : IN std_ulogic;
rst_n : IN std_ulogic;
ser_i : IN std_ulogic;
done_o : OUT std_ulogic);
END COMPONENT sequence_detector_18bit;
COMPONENT lfsr_18bit IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
lfsr_o : OUT std_ulogic_vector(17 DOWNTO 0);
noise_o : OUT std_ulogic;
eoc_po : OUT std_ulogic);
END COMPONENT lfsr_18bit;
-- component ports
SIGNAL clk_i : std_ulogic;
SIGNAL rst_ni : std_ulogic;
SIGNAL done_o : std_ulogic;
SIGNAL noise_o : std_ulogic;
SIGNAL eoc_po : std_ulogic;
SIGNAL en_pi : std_ulogic;
SIGNAL lfsr_o : std_ulogic_vector(17 DOWNTO 0);
-- definition of a clock period
CONSTANT period : time := 20 ns;
-- switch for clock generator
SIGNAL clken_p : boolean := true;
BEGIN -- ARCHITECTURE tbench
-- component instantiation
DUT : sequence_detector_18bit
PORT MAP (
clk => clk_i,
rst_n => rst_ni,
ser_i => noise_o,
done_o => done_o);
LFSR : lfsr_18bit
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
en_pi => en_pi,
lfsr_o => lfsr_o,
noise_o => noise_o,
eoc_po => eoc_po);
-- clock generation
clock_p : PROCESS
BEGIN
WHILE clken_p LOOP
clk_i <= '0'; WAIT FOR period/2;
clk_i <= '1'; WAIT FOR period/2;
END LOOP;
WAIT;
END PROCESS;
-- initial reset, always necessary at the beginning OF a simulation
reset : rst_ni <= '0', '1' AFTER period;
-- process for stimuli generation
stimuli_p : PROCESS
BEGIN
WAIT UNTIL rst_ni = '1'; -- wait until asynchronous reset ...
en_pi <= '1'; -- ... is deactivated
WAIT FOR 250000*period;
clken_p <= false; -- switch clock generator off
WAIT;
END PROCESS;
END ARCHITECTURE tbench;
-------------------------------------------------------------------------------
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