Commit 371ab8f9 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab#8 triangular wave testing

parent 6973db2f
......@@ -12,7 +12,8 @@
SYN_SOURCE_FILES = \
../../src/sequence_detector_qfsm.vhd \
../../src/lfsr_fibonacci.vhd
../../src/lfsr_fibonacci.vhd \
../../src/cntupen_rtl.vhd
# do not delete this line
# -----------------------------------------------------------------------------
......@@ -40,6 +40,7 @@ ARCHITECTURE tbench OF t_sequence_detector IS
noise_o : OUT std_ulogic;
eoc_po : OUT std_ulogic);
END COMPONENT lfsr_fibonacci;
-- component ports
SIGNAL clk_i : std_ulogic;
......@@ -74,6 +75,7 @@ BEGIN -- ARCHITECTURE tbench
lfsr_o => lfsr_o,
noise_o => noise_o,
eoc_po => eoc_po);
-- clock generation
clock_p : PROCESS
......
......@@ -29,7 +29,7 @@ begin
count_ouput : count_o <= count_i + 1 WHEN count_rst = '0' ELSE to_unsigned(0, count_o'length);
count_input : count_i <= to_unsigned(0, count_i'length) WHEN rst_n = '0' ELSE
count_input : count_i <= to_unsigned(0, count_i'length) WHEN rst_n = '0' OR count_rst = '1' ELSE
count_o WHEN rising_edge(clk);
......
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