Commit 3ad99035 authored by Friedrich Beckmann's avatar Friedrich Beckmann
Browse files

de1_adc: added PLL for 65 MSamples/s

parent e6d8d93f
create_clock -period 20.000 -name CLOCK_50 [get_ports CLOCK_50]
# PLL to generate 65 MHz from 50 MHz
create_generated_clock -source altpll:pll_i0|pll|inclk[0] \
-name pll_clk \
-multiply_by 13 \
-divide_by 10 \
-master_clock CLOCK_50 \
[get_pins altpll:pll_i0|pll|clk[0]]
set default_inputs [get_ports KEY0]
set default_inputs [add_to_collection $default_inputs [get_ports ADC_OTR*]]
# The PLL also provides some clock for ADC/DAC Board
set clock_outputs [get_ports ADC_CLK*]
set clock_outputs [add_to_collection $clock_outputs [get_ports DAC_CLK*]]
set clock_outputs [add_to_collection $clock_outputs [get_ports DAC_WRT*]]
set default_outputs [remove_from_collection [all_outputs] [get_ports DAC_D*]]
set default_outputs [remove_from_collection $default_outputs $clock_outputs]
# Default Timing Constrains for Inputs/Outputs
set_input_delay -clock pll_clk 5 $default_inputs
set_output_delay -clock pll_clk 5 $default_outputs
# Special Timing for ADC and DAC Data I/O
set_input_delay -clock pll_clk 12 [get_ports ADC_D*]
set_output_delay -clock pll_clk -clock_fall 10 [get_ports DAC_D*]
# Special Timing for clock outputs
set_output_delay -clock pll_clk 2 $clock_outputs
...@@ -8,3 +8,7 @@ PROGFILEEXT = sof ...@@ -8,3 +8,7 @@ PROGFILEEXT = sof
SOURCE_FILES = ../../src/de1_adc_rtl.vhd SOURCE_FILES = ../../src/de1_adc_rtl.vhd
include ../makefile include ../makefile
# Use the specific sdc file
$(PROJECT).sdc: $(PROJECT)_special.sdc
ln -s $(PROJECT)_special.sdc $(PROJECT).sdc
...@@ -2,6 +2,10 @@ library ieee; ...@@ -2,6 +2,10 @@ library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
-- PLL for 100 MHz speed
library altera_mf;
use altera_mf.all;
entity de1_adc is entity de1_adc is
port ( CLOCK_50 : in std_ulogic; port ( CLOCK_50 : in std_ulogic;
SW : in std_ulogic_vector(9 downto 0); SW : in std_ulogic_vector(9 downto 0);
...@@ -27,18 +31,60 @@ end entity; ...@@ -27,18 +31,60 @@ end entity;
architecture rtl of de1_adc is architecture rtl of de1_adc is
-- Altera PLL
component altpll
generic (
clk0_divide_by : natural;
clk0_duty_cycle : natural;
clk0_multiply_by : natural;
-- clk0_phase_shift : STRING;
-- compensate_clock : STRING;
inclk0_input_frequency : natural;
-- intended_device_family : STRING;
-- lpm_hint : STRING;
-- lpm_type : STRING;
operation_mode : string;
port_inclk0 : string;
port_clk0 : string
);
port (
clk : out std_logic_vector (5 downto 0);
inclk : in std_logic_vector (1 downto 0)
);
end component;
signal pll_inclk : std_logic_vector(1 downto 0);
signal pll_outclk : std_logic_vector(5 downto 0);
signal clk,rst_n : std_ulogic; signal clk,rst_n : std_ulogic;
signal dac_a_dat, dac_b_dat, adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0); signal dac_a_dat, dac_b_dat, adc_a_dat, adc_b_dat : std_ulogic_vector(13 downto 0);
begin begin
clk <= CLOCK_50; pll_i0 : altpll
generic map (
clk0_divide_by => 10,
clk0_duty_cycle => 50,
clk0_multiply_by => 13,
-- clk0_phase_shift => "0",
-- compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
operation_mode => "NORMAL",
port_inclk0 => "PORT_USED",
port_clk0 => "PORT_USED"
)
port map (
inclk => pll_inclk,
clk => pll_outclk
);
pll_inclk(0) <= CLOCK_50;
pll_inclk(1) <= '0';
clk <= pll_outclk(0);
--clk <= CLOCK_50;
rst_n <= KEY0; rst_n <= KEY0;
with SW(1 downto 0) select LEDR <= "00000000" & ADC_OTR_A & ADC_OTR_B when rising_edge(clk);
LEDR <=
adc_b_dat(9 downto 0) when "00",
adc_b_dat(13 downto 4) when "01",
"00000000" & ADC_OTR_A & ADC_OTR_B when others;
DAC_MODE <= '1'; --dual port DAC_MODE <= '1'; --dual port
DAC_CLK_A <= clk; DAC_CLK_A <= clk;
......
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