Commit 3e9a674c authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab#5_cntdnmodm

parent dc3c915f
...@@ -38,11 +38,12 @@ BEGIN ...@@ -38,11 +38,12 @@ BEGIN
next_state_logic : next_state <= to_unsigned(m-1, n) WHEN current_state = 0 ELSE next_state_logic : next_state <= to_unsigned(m-1, n) WHEN current_state = 0 ELSE
current_state - 1; current_state - 1;
state_register : state_register : current_state <= to_unsigned(m-1, n) WHEN rst_ni = '0' ELSE
next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
counter_output : counter_output : count_o <= std_ulogic_vector(current_state);
terminal_count : terminal_count : tc_o <= '1' WHEN current_state = 0 ELSE '0';
END rtl; END rtl;
......
...@@ -90,11 +90,17 @@ BEGIN ...@@ -90,11 +90,17 @@ BEGIN
-- create a frequency of 100 Hz at its output signal tc_100hz_o -- create a frequency of 100 Hz at its output signal tc_100hz_o
-- declare the necessary signals count_modxxx_o and tc_100hz_o -- declare the necessary signals count_modxxx_o and tc_100hz_o
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- prescaler : cntdnmodm prescaler : ENTITY work.cntdnmodm
-- GENERIC MAP ( GENERIC MAP (
-- n => n => 19,
-- m => ) m => 500000)
-- PORT MAP ( PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
en_pi => en_pi,
count_o => OPEN,
tc_o => tc_100hz_o);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- connecting count value to GPIO1 -- connecting count value to GPIO1
......
...@@ -46,6 +46,7 @@ ARCHITECTURE tbench OF t_cntdnmodm IS ...@@ -46,6 +46,7 @@ ARCHITECTURE tbench OF t_cntdnmodm IS
SIGNAL count_mod500e3_o : std_ulogic_vector(18 DOWNTO 0); SIGNAL count_mod500e3_o : std_ulogic_vector(18 DOWNTO 0);
SIGNAL tc_100hz_o : std_ulogic; SIGNAL tc_100hz_o : std_ulogic;
-- definition of a clock period -- definition of a clock period
...@@ -81,6 +82,18 @@ BEGIN -- tbench ...@@ -81,6 +82,18 @@ BEGIN -- tbench
-- instantiate and parameterise the generics to -- instantiate and parameterise the generics to
-- create a frequency of 100 Hz at its output signal tc_100hz_o -- create a frequency of 100 Hz at its output signal tc_100hz_o
-- declare the necessary signals count_modxxx_o and tc_100hz_o -- declare the necessary signals count_modxxx_o and tc_100hz_o
prescaler : cntdnmodm
GENERIC MAP (
n => 19,
m => 500000)
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
en_pi => en_pi,
count_o => count_mod500e3_o,
tc_o => tc_100hz_o);
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
-- prescaler : cntdnmodm -- prescaler : cntdnmodm
-- GENERIC MAP ( -- GENERIC MAP (
...@@ -132,11 +145,15 @@ BEGIN -- tbench ...@@ -132,11 +145,15 @@ BEGIN -- tbench
-- wait for a period of tc_100hz_o ---------------------------------------- -- wait for a period of tc_100hz_o ----------------------------------------
--WAIT UNTIL rising_edge(tc_o);
WAIT UNTIL rising_edge(tc_100hz_o);
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- wait for a period of tc_100hz_o ---------------------------------------- -- wait for a period of tc_100hz_o ----------------------------------------
--WAIT UNTIL rising_edge(tc_o);
WAIT UNTIL rising_edge(tc_100hz_o);
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
......
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