Skip to content

GitLab

Commit 4de75bc9 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab#7 finished

parent 343597b7
Hide whitespace changes
Inline Side-by-side
doc/heartbeat_generator_datasheet.md
View file @ 4de75bc9
......@@ -31,6 +31,7 @@ General Description
| en_pi | std_ulogic | IN | HIGH | enable |
| count_o | std_ulogic_vector | OUT | HIGH | count value |
| heartbeat_o | std_ulogic | OUT | HIGH | heartbeat pulse output |
: Heartbeat Generator - Description of I/O Signals
......@@ -79,8 +80,25 @@ The following results are extracted from
```pure
+--------------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+-------------------------------------------------+
; Fitter Summary ;
+-------------------------------------+------------------------------------------------+
; Fitter Status ; Successful - Thu Apr 22 15:49:45 2021 ;
; Quartus II 32-bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition;
; Revision Name ; de1_heartbeat_gen ;
; Top-level Entity Name ; de1_heartbeat_gen ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
; Timing Models ; Final ;
; Total logic elements ; 62 / 18,752 ( < 1 % ) ;
; Total combinational functions ; 62 / 18,752 ( < 1 % ) ;
; Dedicated logic registers ; 26 / 18,752 ( < 1 % ) ;
; Total registers ; 26 ;
; Total pins ; 12 / 315 ( 4 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 239,616 ( 0 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ;
; Total PLLs ; 0 / 4 ( 0 % ) ;
+-------------------------------------+------------------------------------------------+
```
The following results are extracted from
......@@ -91,18 +109,35 @@ de1_heartbeat_gen.sta.rpt
```pure
+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary ;
; TimeQuest Timing Analyzer Summary ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name ; de1_heartbeat_gen ;
; Device Family ; Cyclone II ;
; Device Name ; EP2C20F484C7 ;
; Timing Models ; Final ;
; Delay Model ; Combined ;
; Rise/Fall Delays ; Unavailable ;
+--------------------+-------------------------------------------------------------------+
-----------------------------------------+
; Clocks ;
+------------+------+--------+-----------+
; Clock Name ; Type ; Period ; Frequency ;
+------------+------+--------+-----------+
; CLOCK_50 ; Base ; 20.000 ; 50.0 MHz ;
+------------+------+--------+-----------+
+-----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary ;
+------------------+-------+-------+----------+---------+---------------------+
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+-------+----------+---------+---------------------+
; Worst-case Slack ; 7.039 ; 0.215 ; 13.239 ; 3.782 ; 8.889 ;
; CLOCK_50 ; 7.039 ; 0.215 ; 13.239 ; 3.782 ; 8.889 ;
; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
; CLOCK_50 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ; 0.000 ;
+------------------+-------+-------+----------+---------+---------------------+
```
Application Note
......@@ -149,10 +184,10 @@ LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY heartbeat_gen IS
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector;
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector;
heartbeat_o : OUT std_ulogic
);
END heartbeat_gen;
......@@ -163,41 +198,45 @@ LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ARCHITECTURE rtl OF heartbeat_gen IS
CONSTANT n : natural := 10;
CONSTANT zero : unsigned(n-1 DOWNTO 0) := (OTHERS => '0');
CONSTANT heartbeat_period : unsigned(n-1 DOWNTO 0) := to_unsigned(833, n);
CONSTANT qrs_width : unsigned(n-1 DOWNTO 0) := to_unsigned(100, n);
CONSTANT st_width
CONSTANT t_width
CONSTANT qt_width
ENTITY heartbeat_gen IS
PORT (clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
count_o : OUT std_ulogic_vector(9 DOWNTO 0);
heartbeat_o : OUT std_ulogic
);
END heartbeat_gen;
SIGNAL next_state, current_state : unsigned(n-1 DOWNTO 0);
ARCHITECTURE rtl OF heartbeat_gen IS
SIGNAL tc_qrs : std_ulogic; -- qrs interval
SIGNAL tc_t : std_ulogic; -- T wave
SIGNAL mux_control : std_ulogic;
SIGNAL next_state : unsigned(9 DOWNTO 0);
SIGNAL current_state : unsigned(9 DOWNTO 0);
BEGIN
next_state_logic :
state_register :
-- output_logic
t_wave : tc_t <=
qrs_complex : tc_qrs <=
output_value : heartbeat_o <=
incrementer : next_state <= current_state + 1 WHEN mux_control = '0' ELSE
to_unsigned(0, current_state'length);
state_register : current_state <= to_unsigned(0, current_state'length) WHEN
rst_ni = '0' ELSE
next_state WHEN rising_edge(clk_i) AND
(en_pi = '1');
counter_output : count_o <= std_ulogic_vector(current_state);
heartbeat_output : heartbeat_o <= '0' WHEN current_state <= to_unsigned(433,
current_state'length) OR
(current_state > to_unsigned(533,
current_state'length) AND
current_state <= to_unsigned(673,
current_state'length)) OR
current_state = to_unsigned(833,
current_state'length) ELSE '1';
mux_control_signal : mux_control <= '1' WHEN current_state = to_unsigned(833,
current_state'length) ELSE '0';
END rtl;
```
......@@ -205,8 +244,9 @@ END rtl;
Revision History
----------------
| **Date** | **Version** | **Change Summary** |
|:----------|:-------------|:--------------------|
| May 2020 | 0.1 | Initial Release |
| April 2021 | 0.2 | Added parameterisation |
| **Date** | **Version** | **Change Summary** |
|:-----------|:-------------|:----------------------------|
| May 2020 | 0.1 | Initial Release |
| April 2021 | 0.2 | Added parameterisation |
| April 2021 | 0.3 | Modified by Manuel and Oran |
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment