Commit 567d14e8 authored by Friedrich Beckmann's avatar Friedrich Beckmann
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audio codec: 48 kHz sampling rate and 50 MHz clock frequency

The original design of the audio echo example runs with 8 kHz
sampling frequency for longer echo time. I changed this to 48 kHz
sampling frequency. Changed the system clock from 24 MHz to 50 MHz
to have default timing constraints.
parent c6f9b2e2
# Pin Configuration
set_location_assignment PIN_B12 -to CLOCK_24
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY0
set_location_assignment PIN_A3 -to I2C_SCLK
set_location_assignment PIN_B3 -to I2C_SDAT
......
......@@ -28,7 +28,8 @@ entity bclk is
end;
architecture rtl of bclk is
signal clk_counter : integer range 0 to 47;
constant max_count : integer := 7;
signal clk_counter : integer range 0 to max_count;
signal bclk_rising_edge_en : std_ulogic;
signal bclk_falling_edge_en : std_ulogic;
begin
......@@ -38,7 +39,7 @@ begin
if reset_ni = '0' then
clk_counter <= 0;
elsif rising_edge(clk_i) then
if clk_counter = 47 then
if clk_counter = max_count then
clk_counter <= 0;
else
clk_counter <= clk_counter + 1;
......@@ -50,10 +51,10 @@ begin
begin
bclk_rising_edge_en <= '0';
bclk_falling_edge_en <= '0';
if clk_counter = 47 then
if clk_counter = max_count then
bclk_rising_edge_en <= '1';
end if;
if clk_counter = 23 then
if clk_counter = max_count / 2 then
bclk_falling_edge_en <= '1';
end if;
end process edge_comb_p;
......
......@@ -22,7 +22,7 @@ use altera.altera_primitives_components.all;
entity de1_audio is
port (
CLOCK_24: in std_ulogic;
CLOCK_50: in std_ulogic;
KEY0: in std_ulogic;
I2C_SCLK: out std_ulogic;
I2C_SDAT: inout std_logic;
......@@ -78,7 +78,7 @@ architecture struct of de1_audio is
begin
reset_n <= KEY0;
clk <= CLOCK_24;
clk <= CLOCK_50;
audio_i0 : audio
port map (
......
......@@ -29,7 +29,8 @@ entity fsgen is
end;
architecture rtl of fsgen is
signal counter : integer range 0 to 63;
constant max_count : integer := 127;
signal counter : integer range 0 to max_count;
begin
fs_cnt_p : process(clk_i, reset_ni)
......@@ -40,7 +41,7 @@ begin
elsif rising_edge(clk_i) then
if bclk_falling_edge_en_i = '1' then
fs_o <= '0';
if counter = 63 then
if counter = max_count then
counter <= 0;
fs_o <= '1';
else
......
......@@ -44,7 +44,7 @@ end;
architecture rtl of i2c is
-- Clock divider section
constant fd_c : integer := 24000000/20000/2; -- 24 MHz system clock, 20 kHz I2C clock
constant fd_c : integer := 50000000/20000/2; -- 50 MHz system clock, 20 kHz I2C clock
signal clk_cnt : integer range 0 to fd_c;
signal clk_cnt_reset, clk_cnt_done : std_ulogic;
......
......@@ -45,7 +45,7 @@ architecture rtl of i2c_write is
X"340A00", -- Digital path control
X"340C61", -- Power Down Control (Everything switched on)
X"340E13", -- Digital Audio Interface Format (Slave Mode, DSP Mode, 16 Bit)
X"34100C", -- Sampling Control (8 kHz Sampling frequency, 12.288 MHz MCLK frequency)
X"341000", -- Sampling Control (48 kHz Sampling frequency, Normal Mode)
X"341201"); -- Active Control (Activate)
begin
......
......@@ -18,7 +18,8 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Master Clock Generator
-- Generate 12 MHz from 24 MHz
-- Generate 12.5 MHz from 50 MHz by dividing by 4
-- Audio Codec expects 12.288 MHz, so we are slightly higher
entity mclk is
port (
......@@ -28,19 +29,19 @@ entity mclk is
end;
architecture rtl of mclk is
signal mclk : std_ulogic;
signal mclk : unsigned(1 downto 0);
begin
mclk_p : process(clk_i, reset_ni)
begin
if reset_ni = '0' then
mclk <= '0';
mclk <= to_unsigned(0, mclk'length);
elsif rising_edge(clk_i) then
mclk <= not mclk;
mclk <= mclk + 1;
end if;
end process mclk_p;
mclk_o <= mclk;
mclk_o <= mclk(1);
end; -- architecture
......
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