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Oran Garrity
vlsilab21_garrity_mikschl
Commits
609f56c6
Commit
609f56c6
authored
Mar 23, 2021
by
Oran Garrity
Browse files
Test Kit 4-bit Adder
parent
40a8feb9
Changes
1
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src/t_add4.vhd
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609f56c6
...
@@ -82,6 +82,18 @@ BEGIN -- tbench
...
@@ -82,6 +82,18 @@ BEGIN -- tbench
ci_i
<=
'0'
;
-- set a value to input ci_i as a 1-bit value
ci_i
<=
'0'
;
-- set a value to input ci_i as a 1-bit value
WAIT
FOR
period
;
-- values are assigned here
WAIT
FOR
period
;
-- values are assigned here
ASSERT
sum_o
=
X"0"
REPORT
"Error: sum is not correct !"
SEVERITY
failure
;
ASSERT
sum_o
=
X"0"
REPORT
"Error: sum is not correct !"
SEVERITY
failure
;
ASSERT
co_o
=
'0'
REPORT
"Error: co is not correct !"
SEVERITY
failure
;
a_i
<=
"0001"
;
-- change value of a_i as binary vector value
b_i
<=
"0001"
;
WAIT
FOR
period
;
ASSERT
sum_o
=
X"2"
REPORT
"Error: sum is not correct !"
SEVERITY
failure
;
ASSERT
co_o
=
'0'
REPORT
"Error: co is not correct !"
SEVERITY
failure
;
a_i
<=
"0010"
;
-- change value of a_i as binary vector value
b_i
<=
"0100"
;
WAIT
FOR
period
;
ASSERT
sum_o
=
X"6"
REPORT
"Error: sum is not correct !"
SEVERITY
failure
;
ASSERT
co_o
=
'0'
REPORT
"Error: co is not correct !"
SEVERITY
failure
;
ASSERT
co_o
=
'0'
REPORT
"Error: co is not correct !"
SEVERITY
failure
;
-- prefix B is the default, hence not necessary to write
-- prefix B is the default, hence not necessary to write
...
...
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