Commit 614a9e74 authored by Friedrich Beckmann's avatar Friedrich Beckmann Committed by Oran Garrity
Browse files

add de1_play

parent 35f21e22
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY[0]
set_location_assignment PIN_R21 -to KEY[1]
set_location_assignment PIN_U22 -to LEDG[0]
set_location_assignment PIN_U21 -to LEDG[1]
set_location_assignment PIN_A3 -to I2C_SCLK
set_location_assignment PIN_B3 -to I2C_SDAT
set_location_assignment PIN_A6 -to AUD_ADCLRCK
set_location_assignment PIN_B6 -to AUD_ADCDAT
set_location_assignment PIN_A5 -to AUD_DACLRCK
set_location_assignment PIN_B5 -to AUD_DACDAT
set_location_assignment PIN_B4 -to AUD_XCK
set_location_assignment PIN_A4 -to AUD_BCLK
# ----------------------------------------------------------------------------
SIM_PROJECT_NAME = de1_play
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
include ../makefile
PROJECT = de1_play
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
SYN_SOURCE_FILES = \
../../src/adcintf.vhd \
../../src/bclk.vhd \
../../src/dacintf.vhd \
../../src/fsgen.vhd \
../../src/i2c_sub.vhd \
../../src/i2c.vhd \
../../src/i2c_write.vhd \
../../src/mclk.vhd \
../../src/audio.vhd \
../../src/tone_rtl.vhd \
../../src/e_falling_edge_detector.vhd \
../../src/a_falling_edge_detector_fsm.vhd \
../../src/play_rtl.vhd \
../../src/count1s_rtl.vhd \
../../src/de1_play_structure.vhd
library IEEE;
use IEEE.std_logic_1164.all;
architecture fsm of falling_edge_detector is
signal q0,q1 : std_ulogic;
begin
q0 <= '1' when rst_ni = '0' else x_i when rising_edge(clk_i);
q1 <= '1' when rst_ni = '0' else q0 when rising_edge(clk_i);
fall_o <= '1' when q1 = '1' and q0 = '0' else '0';
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity count1s is
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_o : out std_ulogic);
end entity;
architecture rtl of count1s is
begin
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
library altera;
use altera.altera_primitives_components.all;
entity de1_play is
port (
CLOCK_50 : in std_ulogic; -- 50 mhz clock
KEY : in std_ulogic_vector(1 downto 0);
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_logic;
AUD_ADCLRCK : out std_ulogic;
AUD_ADCDAT : in std_ulogic;
AUD_DACLRCK : out std_ulogic;
AUD_DACDAT : out std_ulogic;
AUD_XCK : out std_ulogic;
AUD_BCLK : out std_ulogic;
LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0)
LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0)
);
end de1_play;
architecture structure of de1_play is
component audio is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
i2c_sclk_o : out std_ulogic;
i2c_dat_i : in std_ulogic;
i2c_dat_o : out std_ulogic;
aud_adclrck_o : out std_ulogic;
aud_adcdat_i : in std_ulogic;
aud_daclrck_o : out std_ulogic;
aud_dacdat_o : out std_ulogic;
aud_xck_o : out std_ulogic;
aud_bclk_o : out std_ulogic;
adc_data_o : out std_ulogic_vector(15 downto 0);
adc_valid_o : out std_ulogic;
dac_data_i : in std_ulogic_vector(15 downto 0);
dac_strobe_o : out std_ulogic);
end component;
component tone is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
switches_i : in std_ulogic_vector(9 downto 0);
dv_i : in std_ulogic;
audio_i : in std_ulogic_vector(15 downto 0);
audio_o : out std_ulogic_vector(15 downto 0));
end component;
component count1s
port (
clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_o : out std_ulogic);
end component;
component falling_edge_detector
port (
clk_i : in std_ulogic;
rst_ni : in std_ulogic;
x_i : in std_ulogic;
fall_o : out std_ulogic);
end component;
component play is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_i : in std_ulogic;
key_i : in std_ulogic;
led_o : out std_ulogic_vector(4 downto 0));
end component;
signal clk : std_ulogic;
signal rst_n : std_ulogic;
signal key_inv : std_ulogic;
signal key_edge : std_ulogic;
signal one_second_period : std_ulogic;
signal i2c_dat_o : std_ulogic;
signal i2c_dat_i : std_ulogic;
signal adc_valid : std_ulogic;
signal dac_data, adc_data : std_ulogic_vector(15 downto 0);
begin
-- connecting clock generator master clock of synchronous system
clk <= CLOCK_50;
-- connecting asynchronous system reset to digital system
rst_n <= KEY(0);
LEDG <= KEY; -- pushbutton on green LED
-- falling edge detection for KEY1
falling_edge_detect_i0 : falling_edge_detector
port map (
clk_i => clk,
rst_ni => rst_n,
x_i => KEY(1),
fall_o => key_edge);
-- based on the 50 mhz clock, generates an enable signal of period t = 1 sec
count1s_i0 : count1s
port map (
clk => clk,
rst_n => rst_n,
onesec_o => one_second_period);
play_i0 : play
port map (
clk => clk,
rst_n => rst_n,
onesec_i => one_second_period,
key_i => key_edge,
led_o => LEDR);
audio_i0 : audio
port map (
clk_i => clk,
reset_ni => rst_n,
i2c_sclk_o => I2C_SCLK,
i2c_dat_i => i2c_dat_i,
i2c_dat_o => i2c_dat_o,
aud_adclrck_o => AUD_ADCLRCK,
aud_adcdat_i => AUD_ADCDAT,
aud_daclrck_o => AUD_DACLRCK,
aud_dacdat_o => AUD_DACDAT,
aud_xck_o => AUD_XCK,
aud_bclk_o => AUD_BCLK,
adc_data_o => adc_data,
adc_valid_o => adc_valid,
dac_data_i => dac_data,
dac_strobe_o => open);
tone_i0 : tone
port map (
clk => clk,
rst_n => rst_n,
dv_i => adc_valid,
audio_i => adc_data,
audio_o => dac_data,
switches_i => "0000000000");
-- i2c has an open-drain ouput
i2c_dat_i <= I2C_SDAT;
i2c_data_buffer_i : OPNDRN
port map (a_in => i2c_dat_o, a_out => I2C_SDAT);
end structure;
------------------------------------------------------------------
-- module : play
------------------------------------------------------------------
-- author : Friedrich Beckmann
-- company : university of applied sciences augsburg
------------------------------------------------------------------
-- description: Statemachine for LED game
--
------------------------------------------------------------------
-- revisions : 0.1 -
------------------------------------------------------------------
-- 5 LED outputs
-- One one-second enable input
-- KEY input with preceding rising_edge detector
-- step LED4 LED3 LED2 LED1 LED0
-- 1 x - - - -
-- 2 - x - - -
-- 3 - - x - -
-- 4 - - - x -
-- 5 - - - - x
-- 6 x - - - -
-- ... this pattern continues
-- If LED2 is on and KEY is pressed then the pattern continues as follows
-- 1 x - - - -
-- 2 - - - - x
-- ... this pattern continues until
-- KEY is pressed again. Then the previous pattern restarts from LED 2
library ieee;
use ieee.std_logic_1164.all;
entity play is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_i : in std_ulogic;
key_i : in std_ulogic;
led_o : out std_ulogic_vector(4 downto 0));
end play;
architecture rtl of play is
type state_t is (start_s,one_s,chance_s,four_s,last_s,hit0_s,hit1_s);
signal current_state,next_state : state_t;
begin
current_state <= start_s when rst_n = '0' else next_state when rising_edge(clk);
next_p : process(current_state, onesec_i, key_i)
begin
next_state <= current_state;
led_o <= "00000";
case current_state is
when start_s =>
led_o <= "10000";
if onesec_i = '1' then
next_state <= one_s;
end if;
when one_s =>
led_o <= "01000";
if onesec_i = '1' then
next_state <= chance_s;
end if;
when chance_s =>
led_o <= "00100";
if key_i = '1' then
next_state <= hit0_s;
elsif onesec_i = '1' then
next_state <= four_s;
end if;
when four_s =>
led_o <= "00010";
if onesec_i = '1' then
next_state <= last_s;
end if;
when last_s =>
led_o <= "00001";
if onesec_i = '1' then
next_state <= start_s;
end if;
when hit0_s =>
led_o <= "10000";
if key_i = '1' then
next_state <= chance_s;
elsif onesec_i = '1' then
next_state <= hit1_s;
end if;
when hit1_s =>
led_o <= "00001";
if key_i = '1' then
next_state <= chance_s;
elsif onesec_i = '1' then
next_state <= hit0_s;
end if;
when others => null;
end case;
end process;
end architecture rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity t_de1_play is
end t_de1_play;
architecture tbench of t_de1_play is
component de1_play is
port (
CLOCK_50 : in std_ulogic; -- 50 mhz clock
KEY : in std_ulogic_vector(1 downto 0); -- key(1..0)
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_logic;
AUD_ADCLRCK : out std_ulogic;
AUD_ADCDAT : in std_ulogic;
AUD_DACLRCK : out std_ulogic;
AUD_DACDAT : out std_ulogic;
AUD_XCK : out std_ulogic;
AUD_BCLK : out std_ulogic;
LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0)
LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0)
);
end component;
-- definition of a clock period
constant period : time := 10 ns;
-- switch for clock generator
signal clken_p : boolean := true;
signal clk_i : std_ulogic;
signal rst_ni : std_ulogic;
signal key : std_ulogic;
signal ledr : std_ulogic_vector(4 downto 0);
signal i2c_clk, i2c_dat : std_ulogic;
signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic;
signal phase : real := 0.0;
signal test_tone : real;
signal test_tone_quantized : signed(15 downto 0);
signal bit_count : integer range 0 to 31;
begin
-- clock generation
clock_proc : process
begin
while clken_p loop
clk_i <= '0'; wait for period/2;
clk_i <= '1'; wait for period/2;
end loop;
wait;
end process;
-- initial reset, always necessary at the beginning of a simulation
reset : rst_ni <= '0', '1' AFTER period;
stimuli_p : process
begin
key <= '1';
wait until rst_ni = '1';
wait for 20*period;
key <= '0';
wait for 10*period;
key <= '1';
wait for 30*period;
clken_p <= false;
wait;
end process stimuli_p;
de1_play_i0 : de1_play
port map (
CLOCK_50 => clk_i,
KEY(0) => rst_ni,
KEY(1) => key,
I2C_SCLK => i2c_clk,
I2C_SDAT => i2c_dat,
AUD_ADCLRCK => aud_adclrck,
AUD_ADCDAT => aud_adcdat,
AUD_DACLRCK => aud_daclrck,
AUD_DACDAT => aud_dacdat,
AUD_XCK => aud_xck,
AUD_BCLK => aud_bclk,
LEDR => ledr);
aud_adcdat <= test_tone_quantized(bit_count mod 16);
-- Test tone generator for simulating the ADC from the audio codec
phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck);
test_tone <= sin(2*3.14*phase);
test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16);
bit_count <= 31 when falling_edge(aud_daclrck) else
0 when bit_count = 0 else
bit_count - 1 when falling_edge(aud_bclk);
end tbench;
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