Commit 66d4ef9f by Oran Garrity

### Laboratory Exercise 4

parent 4dcfd3d8
 ... ... @@ -30,7 +30,7 @@ BEGIN dflipflop_1 : q1 <= '0' WHEN (rst_ni = '0') ELSE q0 WHEN rising_edge(clk_i); output_logic : fall_o <= ; -- fill in the correct equation here output_logic : fall_o <= NOT q0 AND q1 ; -- fill in the correct equation here END rtl; ... ...
 ... ... @@ -46,7 +46,7 @@ BEGIN d_i => q0, q_o => q1); output_logic : fall_o <= ; -- fill in the correct equation here output_logic : fall_o <= NOT q0 AND q1; -- fill in the correct equation here END structure; ... ...
 ... ... @@ -93,6 +93,20 @@ BEGIN -- tbench -- add another low-active input pulse here ... x_i <= '1'; -- assign a '1' to x_i WAIT FOR period; x_i <= '0'; -- set input to '0' ... WAIT UNTIL rising_edge(clk_i); WAIT UNTIL falling_edge(clk_i); -- Observer: check, if fall_o is assigned to '1' for one clock period ASSERT fall_o = '1' REPORT "Error: Expected fall_o = '1' !" SEVERITY failure; WAIT UNTIL falling_edge(clk_i); ASSERT fall_o = '0' REPORT "Error: Expected fall_o = '0' !" SEVERITY failure; WAIT FOR 6 * period; -- ... for a no. of periods x_i <= '1'; -- assign a '1' to form a WAIT FOR 3 * period; -- low active input pulse ... ...
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