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Oran Garrity
vlsilab21_garrity_mikschl
Commits
68d6f052
Commit
68d6f052
authored
Apr 27, 2021
by
Manuel Mikschl
Browse files
lab#8 simulation of tone_rtl
parent
07f70632
Changes
8
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sim/de1_tone/de1_tone.cr.mti
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07f70632
sim/de1_tone/de1_tone.mpf
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07f70632
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sim/de1_tone/modelsim_sources.tcl
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07f70632
project addfile ../../src/adcintf.vhd
project addfile ../../src/bclk.vhd
project addfile ../../src/dacintf.vhd
project addfile ../../src/fsgen.vhd
project addfile ../../src/i2c_sub.vhd
project addfile ../../src/i2c.vhd
project addfile ../../src/i2c_write.vhd
project addfile ../../src/mclk.vhd
project addfile ../../src/audio.vhd
project addfile ../../src/tone_rtl.vhd
project addfile ../../src/de1_tone.vhd
project addfile ../../src/t_de1_tone.vhd
sim/de1_tone/mproject_created
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07f70632
sim/de1_tone/transcript
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07f70632
# project open de1_tone
# Loading project de1_tone
# vsim work.t_de1_tone(tbench)
# vsim work.t_de1_tone(tbench)
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading ieee.math_real(body)
# Loading work.t_de1_tone(tbench)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading altera.dffeas_pack
# Loading altera.altera_primitives_components
# Loading work.de1_tone(struct)
# Loading work.audio(struct)
# Loading work.i2c_sub(struct)
# Loading work.i2c(rtl)
# Loading work.i2c_write(rtl)
# Loading work.mclk(rtl)
# Loading work.bclk(rtl)
# Loading work.fsgen(rtl)
# Loading work.dacintf(rtl)
# Loading work.adcintf(rtl)
# Loading work.tone(rtl)
# Loading altera.opndrn(behavior)
# add wave *
# run -a
# ** Warning: NUMERIC_STD.TO_SIGNED: vector truncated
# Time: 0 ns Iteration: 0 Instance: /t_de1_tone
#
sim/de1_tone/vsim.wlf
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07f70632
File deleted
src/t_de1_tone.vhd
View file @
68d6f052
...
...
@@ -40,6 +40,18 @@ architecture tbench of t_de1_tone is
);
end
component
;
COMPONENT
tone_rtl
IS
port
(
clk
:
IN
std_ulogic
;
rst_n
:
IN
std_ulogic
;
switches_i
:
in
std_ulogic_vector
(
9
downto
0
);
dv_i
:
in
std_ulogic
;
audio_i
:
in
std_ulogic_vector
(
15
downto
0
);
audio_o
:
out
std_ulogic_vector
(
15
downto
0
)
);
END
component
;
signal
clk
,
reset_n
:
std_ulogic
;
signal
ledr
:
std_ulogic_vector
(
9
downto
0
);
signal
i2c_clk
,
i2c_dat
:
std_ulogic
;
...
...
@@ -55,6 +67,11 @@ architecture tbench of t_de1_tone is
signal
bit_count
:
integer
range
0
to
31
;
signal
switches
:
std_ulogic_vector
(
9
downto
0
);
-- signal for triangular output
SIGNAL
audio_triangular
:
std_ulogic_vector
(
15
DOWNTO
0
);
SIGNAL
audio_i
:
std_ulogic_vector
(
15
DOWNTO
0
);
Signal
dv_i
:
std_ulogic
;
begin
de1_tone_i0
:
de1_tone
...
...
@@ -71,6 +88,19 @@ begin
AUD_BCLK
=>
aud_bclk
,
SW
=>
switches
,
LEDR
=>
ledr
);
-- test tone generator for triangular signal
MUV
:
tone_rtl
PORT
MAP
(
clk
=>
clk
,
rst_n
=>
reset_n
,
switches_i
=>
"0000000000"
,
dv_i
=>
'1'
,
audio_i
=>
"0000000000000000"
,
audio_o
=>
audio_triangular
);
clock_p
:
process
begin
...
...
@@ -103,6 +133,9 @@ begin
0
when
bit_count
=
0
else
bit_count
-
1
when
falling_edge
(
aud_bclk
);
end
;
-- architecture
src/tone_rtl.vhd
View file @
68d6f052
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
USE
IEEE
.
numeric_std
.
ALL
;
entity
tone
is
port
(
clk
:
in
std_ulogic
;
...
...
@@ -13,35 +14,41 @@ end entity;
architecture
rtl
of
tone
IS
SIGNAL
incrementer
:
std_ulogic
;
SIGNAL
count_o
:
unsigned
(
1
3
DOWNTO
0
);
SIGNAL
count_i
:
unsigned
(
1
3
DOWNTO
0
);
SIGNAL
count_o
:
unsigned
(
1
4
DOWNTO
0
);
SIGNAL
count_i
:
unsigned
(
1
4
DOWNTO
0
);
SIGNAL
count_rst
:
std_ulogic
;
SIGNAL
current_state
:
signed
(
15
DOWNTO
0
);
SIGNAL
next_state
:
signed
(
15
DOWNTO
0
);
begin
-- audio_o <= audio_i when rising_edge(clk) and dv_i = '1';
-- phase counter
count_ouput
:
count_o
<=
count_i
+
1
WHEN
count_rst
=
'0'
ELSE
to_unsigned
(
0
,
count_o
'length
);
count_input
:
count_i
<=
to_unsigned
(
0
,
current_state
'length
)
WHEN
rst_n
=
'0'
ELSE
count_ouput
:
count_o
<=
count_i
+
1
WHEN
count_rst
=
'0'
ELSE
to_unsigned
(
0
,
count_o
'length
);
count_input
:
count_i
<=
to_unsigned
(
0
,
count_i
'length
)
WHEN
rst_n
=
'0'
ELSE
count_o
WHEN
rising_edge
(
clk
);
count_reset
:
count_rst
<=
'1'
WHEN
count_o
=
to_unsigned
(
8332
,
count_o
'length
)
ELSE
'0'
;
incrementer_signal
:
incrementer
<=
'1'
WHEN
count_o
<=
to_unsigned
(
2083
,
count_o
'length
)
AND
count_o
>
to_unsigned
(
6249
,
count_o
'length
)
ELSE
'0'
;
incrementer_signal
:
incrementer
<=
'1'
WHEN
count_o
<=
to_unsigned
(
2083
,
count_o
'length
)
OR
count_o
>
to_unsigned
(
6249
,
count_o
'length
)
ELSE
'0'
;
-- output counter
state_register
:
current_state
<=
to_signed
(
0
,
current_state
'length
)
WHEN
rst_n
=
'0'
ELSE
next_state
WHEN
rising_edge
(
clk
);
next_state_output
:
next_state
<=
current_state
+
0
.
00048007681
WHEN
incrementer
=
'0'
ELSE
current_state
-
0
.
00048007681
;
next_state_output
:
next_state
<=
current_state
+
1
WHEN
incrementer
=
'1'
ELSE
current_state
-
1
;
-- 0.00048007681
audio_output
:
audio_o
<=
std_ulogic_vector
(
current_state
);
...
...
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