Skip to content
GitLab
Menu
Projects
Groups
Snippets
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
Open sidebar
Oran Garrity
vlsilab21_garrity_mikschl
Commits
69670945
Commit
69670945
authored
Mar 22, 2021
by
Oran Garrity
Browse files
lab#2_mux2to1
parent
62360a61
Changes
4
Hide whitespace changes
Inline
Side-by-side
sim/mux2to1/makefile.sources
View file @
69670945
...
...
@@ -11,7 +11,10 @@
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES
=
\
../../src/mux2to1_rtl.vhd
\
../../src/and2gate_equation.vhd
\
../../src/or2gate_equation.vhd
\
../../src/invgate_equation.vhd
\
../../src/mux2to1_structure_errors.vhd
\
# do not delete this line
# -----------------------------------------------------------------------------
src/#t_mux2to1.vhd#
0 → 100644
View file @
69670945
-------------------------------------------------------------------------------
-- Module : t_mux2to1
-------------------------------------------------------------------------------
-- Author : <haf@fh-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2011 <haf@fh-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "mux2to1"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_mux2to1 IS
END t_mux2to1;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_mux2to1 IS
COMPONENT mux2to1
PORT (
a_i : IN std_ulogic;
b_i : IN std_ulogic;
sel_i : IN std_ulogic;
y_o : OUT std_ulogic);
END COMPONENT;
-- definition of a clock period
CONSTANT period : time := 10 ns;
-- component ports
SIGNAL a_i : std_ulogic;
SIGNAL b_i : std_ulogic;
SIGNAL sel_i : std_ulogic;
SIGNAL y_o : std_ulogic;
BEGIN -- tbench
-- component instantiation
MUV : mux2to1
PORT MAP (
a_i => a_i,
b_i => b_i,
sel_i => sel_i,
y_o => y_o);
stimuli_p : PROCESS
BEGIN
-- 000
a_i <= '0'; -- set a value to input a_i
b_i <= '0'; -- set a value to input b_i
sel_i <= '0'; -- set a value to input ci_i
WAIT FOR period; -- values are assigned here
-- 001
a_i <= '1'; -- change value of a_i
WAIT FOR period;
-- 010
a_i <= '0'; -- change value of a_i
b_i <= '1'; -- change value of b_i
WAIT FOR period;
-- 010
a_i <= '0';
b_i <= '1';
WAIT FOR period;
-- add the missing stimuli here ...
WAIT;
END PROCESS;
END tbench;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/mux2to1_structure_errors.vhd
View file @
69670945
-------------------------------------------------------------------------------
-- Module : mux2to1
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 2-to-1 multiplexer
-- function modelled as structure of basic logic gates
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
mux2to1
IS
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
sel_i
:
IN
std_ulogic
;
-- y_o : OUT std_ulogic; -- kein ; nach letztem Signal
y_o
:
OUT
std_ulogic
);
END
mux21
;
ARCHITECTURE
structure
OF
mux2to1
IS
COMPONENT
invgate
PORT
(
a_i
:
IN
std_ulogic
;
y_o
:
OUT
std_ulogic
);
END
COMPONENT
;
COMPONENT
or2gate
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
y_o
:
std_ulogic
);
END
COMPONENT
;
SIGNAL
p1
:
std_ulogic
;
SIGNAL
p2
:
std_ulogic
;
SIGNAL
p3
:
std_ulogic
;
BEGIN
inv_gate_1
:
invgate
PORT
MAP
(
a_i
=>
sel_i
,
y_o
<=
p2
);
and2_gate_1
:
and2gate
PORT
MAP
(
a_i
=>
a_i
,
b_i
=>
p2
y_o
=>
p0
);
and2_gate_2
:
and2gate
PORT
MAP
(
a_i
=>
b_i
,
b_i
=>
sel_i
,
y_o
=>
p1
);
or2_gate_1
:
or2gate
PORT
MAP
(
a_i
=>
p0
,
b_i
=>
p1
,
y_o
=>
p3
);
END
struct
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : mux2to1
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 2-to-1 multiplexer
-- function modelled as structure of basic logic gates
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
mux2to1
IS
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
sel_i
:
IN
std_ulogic
;
-- y_o : OUT std_ulogic; -- kein ; nach letztem Signal
y_o
:
OUT
std_ulogic
);
END
mux2to1
;
ARCHITECTURE
structure
OF
mux2to1
IS
COMPONENT
invgate
PORT
(
a_i
:
IN
std_ulogic
;
y_o
:
OUT
std_ulogic
);
END
COMPONENT
;
COMPONENT
or2gate
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
y_o
:
OUT
std_ulogic
);
END
COMPONENT
;
COMPONENT
and2gate
PORT
(
a_i
:
IN
std_ulogic
;
b_i
:
IN
std_ulogic
;
y_o
:
OUT
std_ulogic
);
END
COMPONENT
;
SIGNAL
p0
:
std_ulogic
;
SIGNAL
p1
:
std_ulogic
;
SIGNAL
p2
:
std_ulogic
;
SIGNAL
p3
:
std_ulogic
;
BEGIN
inv_gate_1
:
invgate
PORT
MAP
(
a_i
=>
sel_i
,
y_o
=>
p2
);
and2_gate_1
:
and2gate
PORT
MAP
(
a_i
=>
a_i
,
b_i
=>
p2
,
y_o
=>
p0
);
and2_gate_2
:
and2gate
PORT
MAP
(
a_i
=>
b_i
,
b_i
=>
sel_i
,
y_o
=>
p1
);
or2_gate_1
:
or2gate
PORT
MAP
(
a_i
=>
p0
,
b_i
=>
p1
,
y_o
=>
y_o
);
END
structure
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/or2gate_equation.vhd
View file @
69670945
-------------------------------------------------------------------------------
-- Module : or2gate
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 2-input OR Gate
-- function modelled by logic equation
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : or2gate
-------------------------------------------------------------------------------
-- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg
-------------------------------------------------------------------------------
-- Description: 2-input OR Gate
-- function modelled by logic equation
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
or2gate
IS
PORT
(
a_i
:
IN
std_ulogic
;
-- data input a
b_i
:
IN
std_ulogic
;
-- data input b
y_o
:
OUT
std_ulogic
-- data output y
);
END
or2gate
;
ARCHITECTURE
equation
OF
and2gate
IS
BEGIN
y_o
<=
a_i
OR
b_i
;
END
equation
;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
Write
Preview
Supports
Markdown
0%
Try again
or
attach a new file
.
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment