Commit 69670945 authored by Oran Garrity's avatar Oran Garrity
Browse files

lab#2_mux2to1

parent 62360a61
...@@ -11,7 +11,10 @@ ...@@ -11,7 +11,10 @@
## ---------------------------------------------------------------------------- ## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \ SYN_SOURCE_FILES = \
../../src/mux2to1_rtl.vhd \ ../../src/and2gate_equation.vhd \
../../src/or2gate_equation.vhd \
../../src/invgate_equation.vhd \
../../src/mux2to1_structure_errors.vhd \
# do not delete this line # do not delete this line
# ----------------------------------------------------------------------------- # -----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Module : t_mux2to1
-------------------------------------------------------------------------------
-- Author : <haf@fh-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2011 <haf@fh-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "mux2to1"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_mux2to1 IS
END t_mux2to1;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_mux2to1 IS
COMPONENT mux2to1
PORT (
a_i : IN std_ulogic;
b_i : IN std_ulogic;
sel_i : IN std_ulogic;
y_o : OUT std_ulogic);
END COMPONENT;
-- definition of a clock period
CONSTANT period : time := 10 ns;
-- component ports
SIGNAL a_i : std_ulogic;
SIGNAL b_i : std_ulogic;
SIGNAL sel_i : std_ulogic;
SIGNAL y_o : std_ulogic;
BEGIN -- tbench
-- component instantiation
MUV : mux2to1
PORT MAP (
a_i => a_i,
b_i => b_i,
sel_i => sel_i,
y_o => y_o);
stimuli_p : PROCESS
BEGIN
-- 000
a_i <= '0'; -- set a value to input a_i
b_i <= '0'; -- set a value to input b_i
sel_i <= '0'; -- set a value to input ci_i
WAIT FOR period; -- values are assigned here
-- 001
a_i <= '1'; -- change value of a_i
WAIT FOR period;
-- 010
a_i <= '0'; -- change value of a_i
b_i <= '1'; -- change value of b_i
WAIT FOR period;
-- 010
a_i <= '0';
b_i <= '1';
WAIT FOR period;
-- add the missing stimuli here ...
WAIT;
END PROCESS;
END tbench;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Module : mux2to1 -- Module : mux2to1
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Author : Johann Faerber -- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg -- Company : University of Applied Sciences Augsburg
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: 2-to-1 multiplexer -- Description: 2-to-1 multiplexer
-- function modelled as structure of basic logic gates -- function modelled as structure of basic logic gates
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : see end of file -- Revisions : see end of file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
ENTITY mux2to1 IS ENTITY mux2to1 IS
PORT (a_i : IN std_ulogic; PORT (a_i : IN std_ulogic;
b_i : IN std_ulogic; b_i : IN std_ulogic;
sel_i : IN std_ulogic; sel_i : IN std_ulogic;
-- y_o : OUT std_ulogic; -- kein ; nach letztem Signal -- y_o : OUT std_ulogic; -- kein ; nach letztem Signal
y_o : OUT std_ulogic y_o : OUT std_ulogic
); );
END mux21; END mux2to1;
ARCHITECTURE structure OF mux2to1 IS ARCHITECTURE structure OF mux2to1 IS
COMPONENT invgate COMPONENT invgate
PORT ( PORT (
a_i : IN std_ulogic; a_i : IN std_ulogic;
y_o : OUT std_ulogic); y_o : OUT std_ulogic);
END COMPONENT; END COMPONENT;
COMPONENT or2gate COMPONENT or2gate
PORT ( PORT (
a_i : IN std_ulogic; a_i : IN std_ulogic;
b_i : IN std_ulogic; b_i : IN std_ulogic;
y_o : std_ulogic); y_o : OUT std_ulogic);
END COMPONENT; END COMPONENT;
SIGNAL p1 : std_ulogic; COMPONENT and2gate
SIGNAL p2 : std_ulogic; PORT (
SIGNAL p3 : std_ulogic; a_i : IN std_ulogic;
b_i : IN std_ulogic;
BEGIN y_o : OUT std_ulogic);
END COMPONENT;
inv_gate_1 : invgate
PORT MAP ( SIGNAL p0 : std_ulogic;
a_i => sel_i, SIGNAL p1 : std_ulogic;
y_o <= p2); SIGNAL p2 : std_ulogic;
SIGNAL p3 : std_ulogic;
and2_gate_1 : and2gate BEGIN
PORT MAP (
a_i => a_i, inv_gate_1 : invgate
b_i => p2 PORT MAP (
y_o => p0); a_i => sel_i,
y_o => p2);
and2_gate_2 : and2gate
PORT MAP (
a_i => b_i, and2_gate_1 : and2gate
b_i => sel_i, PORT MAP (
y_o => p1); a_i => a_i,
b_i => p2,
or2_gate_1 : or2gate y_o => p0);
PORT MAP (
a_i => p0, and2_gate_2 : and2gate
b_i => p1, PORT MAP (
y_o => p3); a_i => b_i,
b_i => sel_i,
y_o => p1);
END struct
or2_gate_1 : or2gate
PORT MAP (
------------------------------------------------------------------------------- a_i => p0,
-- Revisions: b_i => p1,
-- ---------- y_o => y_o);
-- $Id:$
-------------------------------------------------------------------------------
END structure;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Module : or2gate -- Module : or2gate
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Author : Johann Faerber -- Author : Johann Faerber
-- Company : University of Applied Sciences Augsburg -- Company : University of Applied Sciences Augsburg
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: 2-input OR Gate -- Description: 2-input OR Gate
-- function modelled by logic equation -- function modelled by logic equation
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Revisions : see end of file -- Revisions : see end of file
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
-------------------------------------------------------------------------------
-- Revisions: ENTITY or2gate IS
-- ---------- PORT (a_i : IN std_ulogic; -- data input a
-- $Id:$ b_i : IN std_ulogic; -- data input b
------------------------------------------------------------------------------- y_o : OUT std_ulogic -- data output y
);
END or2gate;
ARCHITECTURE equation OF and2gate IS
BEGIN
y_o <= a_i OR b_i;
END equation;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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