Commit 6973db2f authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab#9_sequence_detector_101_sim

parent c2d2b9c7
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with ModelSim,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# assign variable PROJECT with the top level project name
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of testbench t_$(PROJECT).vhd
###################################################################
PROJECT = sequence_detector
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile.sources
## ----------------------------------------------------------------------------
## Author : Johann Faerber
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
## Attention !!!
## -------------
## Do not forget a new line after the final source file !
## ----------------------------------------------------------------------------
SYN_SOURCE_FILES = \
../../src/sequence_detector_qfsm.vhd \
../../src/lfsr_fibonacci.vhd
# do not delete this line
# -----------------------------------------------------------------------------
......@@ -6,6 +6,7 @@
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lfsr_fibonacci IS
PORT (
......@@ -26,16 +27,20 @@ ARCHITECTURE rtl OF lfsr_fibonacci IS
SIGNAL count_next_state : unsigned(3 DOWNTO 0);
SIGNAL count_current_state : unsigned(3 DOWNTO 0);
SIGNAL period_output : std_ulogic;
BEGIN
-- counter for eoc_po
count_next_state <= count_current_state + 1;
count_next_state <= count_current_state + 1 WHEN eoc_po = '0' ELSE
count_current_state + 2;
count_current_state <= "0000" WHEN rst_ni = '0' ELSE
count_next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
eoc_po <= '1' WHEN count_current_state = to_unsigned(15, count_current_state'length) ELSE '0';
period_output <= '1' WHEN count_current_state = to_unsigned(15, count_current_state'length) ELSE '0';
eoc_po <= period_output WHEN rising_edge(clk_i);
-- next state logic
d(0) <= q(1);
......
<?xml version='1.0'?>
<!DOCTYPE qfsmproject SYSTEM 'qfsm.dtd'>
<qfsmproject version="0.55" author="Qfsm">
<machine nummooreout="1" transfontitalic="0" draw_it="1" statefontsize="8" transfont="Helvetica" statefontitalic="0" author="" description="sequence detector which is detecting '101'" version="" name="sequence_detector" arrowtype="1" numbits="2" statefontweight="50" statefont="Helvetica" numin="1" transfontsize="8" transfontweight="50" type="0" numout="0" initialstate="0">
<outputnames_moore>done_o</outputnames_moore>
<inputnames>ser_i</inputnames>
<outputnames></outputnames>
<itransition ypos="232" endx="300" xpos="240" endy="232"/>
<state pencolor="0" exit_actions="" radius="40" description="" finalstate="0" entry_actions="" moore_outputs="0" ypos="232" code="0" xpos="340" linewidth="1">State_0</state>
<state pencolor="0" exit_actions="" radius="40" description="" finalstate="0" entry_actions="" moore_outputs="0" ypos="231" code="1" xpos="572" linewidth="1">State_1</state>
<state pencolor="0" exit_actions="" radius="40" description="" finalstate="0" entry_actions="" moore_outputs="0" ypos="231" code="2" xpos="790" linewidth="1">State_2</state>
<state pencolor="0" exit_actions="" radius="40" description="" finalstate="0" entry_actions="" moore_outputs="1" ypos="231" code="3" xpos="1033" linewidth="1">State_3</state>
<transition c1x="430.6664189491514" c2y="231.2758626028395" c1y="231.5517252056789" description="" straight="1" type="0" ypos="231.8275878085184" endx="532" xpos="379.999628423727" endy="231" c2x="481.3332094745757">
<from>0</from>
<to>1</to>
<inputs default="0" any="0" invert="0">1</inputs>
<outputs></outputs>
</transition>
<transition c1x="315.0767945562245" c2y="168.4324023730532" c1y="114.6167225265568" description="" straight="1" type="0" ypos="192.0552868266996" endx="367.2864627823669" xpos="342.1023533249106" endy="202.7519411101095" c2x="441.7799613476965">
<from>0</from>
<to>0</to>
<inputs default="0" any="0" invert="0">0</inputs>
<outputs></outputs>
</transition>
<transition c1x="658" c2y="231" c1y="231" description="" straight="1" type="0" ypos="231" endx="750" xpos="612" endy="231" c2x="704">
<from>1</from>
<to>2</to>
<inputs default="0" any="0" invert="0">0</inputs>
<outputs></outputs>
</transition>
<transition c1x="540.9417377698194" c2y="162.1708472978315" c1y="115.0888946336835" description="" straight="1" type="0" ypos="191.0000000000008" endx="597.7115105158861" xpos="572.000008" endy="200.3582274176007" c2x="670.2982590807262">
<from>1</from>
<to>1</to>
<inputs default="0" any="0" invert="0">1</inputs>
<outputs></outputs>
</transition>
<transition c1x="884.339096607142" c2y="230.2160252906162" c1y="230.6080126453081" description="" straight="1" type="0" ypos="231" endx="993.0172898214258" xpos="830" endy="229.8240379359243" c2x="938.6781932142839">
<from>2</from>
<to>3</to>
<inputs default="0" any="0" invert="0">1</inputs>
<outputs></outputs>
</transition>
<transition c1x="614.6584218042565" c2y="317.4081041089424" c1y="295.1608671768353" description="" straight="0" type="0" ypos="257.3401843147407" endx="377.1390676354104" xpos="759.8969322117249" endy="246.8556270541642" c2x="483.661948055407">
<from>2</from>
<to>0</to>
<inputs default="0" any="0" invert="0">0</inputs>
<outputs></outputs>
</transition>
<transition c1x="860.2764967597994" c2y="388.1929808884502" c1y="335.8446955117523" description="" straight="0" type="0" ypos="251.858000378159" endx="365.7276834569309" xpos="998.8687266539216" endy="262.6281945915844" c2x="476.829730827329">
<from>3</from>
<to>0</to>
<inputs default="0" any="1" invert="0">x</inputs>
<outputs></outputs>
</transition>
</machine>
</qfsmproject>
-- This file was generated by
-- Qfsm Version 0.55
-- (C) Stefan Duffner, Rainer Strobel, Aaron Erhardt
-- Inputs: ser_i
-- State/Output done_o
-- State_0 0
-- State_1 0
-- State_2 0
-- State_3 1
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY sequence_detector IS
PORT (clk: IN std_ulogic;
rst_n: IN std_ulogic;
ser_i: IN std_ulogic;
done_o: OUT std_ulogic);
END sequence_detector;
ARCHITECTURE behave OF sequence_detector IS
TYPE state_type IS (State_0, State_1, State_2, State_3);
SIGNAL next_state, current_state : state_type;
BEGIN
state_register: PROCESS (rst_n, clk)
BEGIN
IF rst_n='0' THEN
current_state <= State_0;
ELSIF rising_edge(clk) THEN
current_state <= next_state;
END IF;
END PROCESS;
next_state_and_output_logic: PROCESS (current_state, ser_i)
VARIABLE temp_input : std_ulogic_vector(0 DOWNTO 0);
VARIABLE temp_output : std_ulogic_vector(0 DOWNTO 0);
BEGIN
temp_input(0) := ser_i;
CASE current_state IS
WHEN State_0 => temp_output := "0";
IF temp_input="1" THEN
next_state <= State_1;
ELSIF temp_input="0" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_1 => temp_output := "0";
IF temp_input="0" THEN
next_state <= State_2;
ELSIF temp_input="1" THEN
next_state <= State_1;
ELSE
next_state <= current_state;
END IF;
WHEN State_2 => temp_output := "0";
IF temp_input="1" THEN
next_state <= State_3;
ELSIF temp_input="0" THEN
next_state <= State_0;
ELSE
next_state <= current_state;
END IF;
WHEN State_3 => temp_output := "1";
next_state <= State_0;
WHEN OTHERS => temp_output := (OTHERS =>'X');
next_state <= State_0;
END CASE;
done_o <= temp_output(0);
END PROCESS;
END behave;
-------------------------------------------------------------------------------
-- Module :
-------------------------------------------------------------------------------
-- Author : <johann.faerber@hs-augsburg.de>
-- Company : University of Applied Sciences Augsburg
-- Copyright (c) 2021 <johann.faerber@hs-augsburg.de>
-------------------------------------------------------------------------------
-- Description: Testbench for design "sequence_detector"
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-------------------------------------------------------------------------------
ENTITY t_sequence_detector IS
END ENTITY t_sequence_detector;
-------------------------------------------------------------------------------
ARCHITECTURE tbench OF t_sequence_detector IS
COMPONENT sequence_detector IS
PORT (
clk : IN std_ulogic;
rst_n : IN std_ulogic;
ser_i : IN std_ulogic;
done_o : OUT std_ulogic);
END COMPONENT sequence_detector;
COMPONENT lfsr_fibonacci IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
lfsr_o : OUT std_ulogic_vector(3 DOWNTO 0);
noise_o : OUT std_ulogic;
eoc_po : OUT std_ulogic);
END COMPONENT lfsr_fibonacci;
-- component ports
SIGNAL clk_i : std_ulogic;
SIGNAL rst_ni : std_ulogic;
SIGNAL done_o : std_ulogic;
SIGNAL noise_o : std_ulogic;
SIGNAL eoc_po : std_ulogic;
SIGNAL en_pi : std_ulogic;
SIGNAL lfsr_o : std_ulogic_vector(3 DOWNTO 0);
-- definition of a clock period
CONSTANT period : time := 20 ns;
-- switch for clock generator
SIGNAL clken_p : boolean := true;
BEGIN -- ARCHITECTURE tbench
-- component instantiation
DUT : sequence_detector
PORT MAP (
clk => clk_i,
rst_n => rst_ni,
ser_i => noise_o,
done_o => done_o);
LFSR : lfsr_fibonacci
PORT MAP (
clk_i => clk_i,
rst_ni => rst_ni,
en_pi => en_pi,
lfsr_o => lfsr_o,
noise_o => noise_o,
eoc_po => eoc_po);
-- clock generation
clock_p : PROCESS
BEGIN
WHILE clken_p LOOP
clk_i <= '0'; WAIT FOR period/2;
clk_i <= '1'; WAIT FOR period/2;
END LOOP;
WAIT;
END PROCESS;
-- initial reset, always necessary at the beginning OF a simulation
reset : rst_ni <= '0', '1' AFTER period;
-- process for stimuli generation
stimuli_p : PROCESS
BEGIN
WAIT UNTIL rst_ni = '1'; -- wait until asynchronous reset ...
en_pi <= '1'; -- ... is deactivated
WAIT FOR 100*period;
clken_p <= false; -- switch clock generator off
WAIT;
END PROCESS;
END ARCHITECTURE tbench;
-------------------------------------------------------------------------------
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