Commit 728570b0 authored by Oran Garrity's avatar Oran Garrity
Browse files

Lab 6 - Extending the Calculator (Part 1)

parent 9a555374
......@@ -28,24 +28,24 @@ ARCHITECTURE structure OF de1_calculator IS
segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
END COMPONENT;
SIGNAL a : unsigned(2 DOWNTO 0);
SIGNAL b : unsigned(2 DOWNTO 0);
SIGNAL a : unsigned(3 DOWNTO 0);
SIGNAL b : unsigned(3 DOWNTO 0);
SIGNAL sum : unsigned(3 DOWNTO 0);
BEGIN
-- connecting switches to operands
a <= unsigned(SW(2 DOWNTO 0));
b <= unsigned(SW(6 DOWNTO 4));
a <= unsigned(SW(3 DOWNTO 0));
b <= unsigned(SW(7 DOWNTO 4));
-- add the operands
sum <= resize(a, sum'length) + resize(b, sum'length);
-- connecting operands to LEDs
LEDR(2 DOWNTO 0) <= SW(2 DOWNTO 0);
LEDR(3) <= '0';
LEDR(6 DOWNTO 4) <= SW(6 DOWNTO 4);
LEDR(7) <= '0';
LEDR(3 DOWNTO 0) <= SW(3 DOWNTO 0);
-- LEDR(3) <= '0';
LEDR(7 DOWNTO 4) <= SW(7 DOWNTO 4);
-- LEDR(7) <= '0';
-- display result on HEX0
result_sum : binto7segment
......
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