Commit 7ba63ed8 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

Simulation of cntdn complete

parent 12a1a407
......@@ -26,16 +26,19 @@ END cntdn;
ARCHITECTURE rtl OF cntdn IS
SIGNAL next_state, current_state : unsigned(3 DOWNTO 0);
BEGIN
incrementer :
incrementer : next_state <= current_state - 1;
state_register :
state_register : current_state <= "1111" WHEN rst_ni = '0' ELSE
next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
counter_output :
counter_output : count_o <= std_ulogic_vector(current_state);
terminal_output :
terminal_output : tc_o <= (NOT current_state(0)) AND (NOT current_state(1)) AND (NOT current_state(2))
AND (NOT current_state(3));
END rtl;
......
......@@ -35,7 +35,7 @@ BEGIN
-- synthesisable construct of a d-type register with synchronrous enable
state_register : current_state <= "0000" WHEN rst_ni = '0' ELSE
state_register : current_state <= "1111" WHEN rst_ni = '0' ELSE
next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
......
......@@ -85,29 +85,36 @@ BEGIN -- tbench
-- 2. activate enable
-- 3. Wait for a full counting cycle
---------------------------------------------------------------------------
en_pi <= '1';
WAIT FOR 15 * period;
ASSERT count_o = X"0" REPORT "Error: Expected count_o = 0 !" SEVERITY failure;
ASSERT tc_o = '1' REPORT "Error: Expected tc_o = 1 !" SEVERITY failure;
---------------------------------------------------------------------------
WAIT FOR 5 * period;
---------------------------------------------------------------------------
-- 4. After another five periods: Deactivate Enable
---------------------------------------------------------------------------
en_pi <= '0';
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- 5. After another three periods: Activate Enable
-- 6. Simulate another complete counting cycle
---------------------------------------------------------------------------
WAIT FOR 3 * period; -- wait for a no. of count values
en_pi <= '1';
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- 7. Simulate until tc_o = 1 again
---------------------------------------------------------------------------
WAIT FOR 10 * period;
ASSERT count_o = X"0" REPORT "Error: Expected count_o = 0 !" SEVERITY failure;
ASSERT tc_o = '1' REPORT "Error: Expected tc_o = 1 !" SEVERITY failure;
---------------------------------------------------------------------------
WAIT FOR 2 * period;
clken_p <= false; -- switch clock generator off
......
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