lab#2_binto7segment

src/binto7segment_truthtable.vhd

@@ -42,17 +42,17 @@ BEGIN
     -- index      |             number displayed
     -- 6543210    |
     --------------------------------------------
-      "1111110" WHEN "0000",    -- 0
-      "0110000" WHEN "0001",    -- 1
-      "1101101" WHEN "0010",    -- 2
-      "1111001" WHEN "0011",    -- 3
-      "0110011" WHEN "0100",    -- 4
-      "1011011" WHEN "0101",    -- 5
-      "1111101" WHEN "0110",    -- 6
-      "1110000" WHEN "0111",    -- 7
-      "1111111" WHEN "1000",    -- 8
-      "1111011" WHEN "1001",    -- 9
-      "1001000" WHEN OTHERS;    -- displays Symbol 'E' for ERROR
+      "1000000" WHEN "0000",    -- 0
+      "1111001" WHEN "0001",    -- 1
+      "0100100" WHEN "0010",    -- 2
+      "0110000" WHEN "0011",    -- 3
+      "0011001" WHEN "0100",    -- 4
+      "0010010" WHEN "0101",    -- 5
+      "0000010" WHEN "0110",    -- 6
+      "1111000" WHEN "0111",    -- 7
+      "0000000" WHEN "1000",    -- 8
+      "0010000" WHEN "1001",    -- 9
+      "0000110" WHEN OTHERS;    -- displays Symbol 'E' for ERROR
 
 END truthtable;
 -------------------------------------------------------------------------------

src/de1_binto7segment_structure.vhd

+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_binto7segment IS
+  PORT (
+    SW   : IN  std_ulogic_vector(3 DOWNTO 0); -- Toggle Switch[3:0]
+    LEDR : OUT std_ulogic_vector(3 DOWNTO 0); -- LED Red[3:0]
+    HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0
+    );
+END de1_binto7segment;
+
+
+ARCHITECTURE structure OF de1_binto7segment IS
+  COMPONENT binto7segment
+    PORT (
+      bin_i      : IN  std_ulogic_vector(3 DOWNTO 0);
+      segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
+  END COMPONENT;
+
+  
+BEGIN
+-- connecting device under test with peripheral elements
+DUT : binto7segment
+  PORT MAP (
+    bin_i      => SW,
+    segments_o => HEX0);
+
+-- connect switches to red LEDs
+LEDR <= SW;
+
+END structure;