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Oran Garrity
vlsilab21_garrity_mikschl
Commits
834fb1c7
Commit
834fb1c7
authored
Mar 22, 2021
by
Manuel Mikschl
Browse files
lab#2_binto7segment
parent
17fba0a5
Changes
2
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src/binto7segment_truthtable.vhd
View file @
834fb1c7
...
...
@@ -42,17 +42,17 @@ BEGIN
-- index | number displayed
-- 6543210 |
--------------------------------------------
"1
11111
0"
WHEN
"0000"
,
-- 0
"
0
1100
00
"
WHEN
"0001"
,
-- 1
"
1101101
"
WHEN
"0010"
,
-- 2
"
11
1100
1
"
WHEN
"0011"
,
-- 3
"011001
1
"
WHEN
"0100"
,
-- 4
"
1011011
"
WHEN
"0101"
,
-- 5
"
11111
01"
WHEN
"0110"
,
-- 6
"111
0
000"
WHEN
"0111"
,
-- 7
"
1111111
"
WHEN
"1000"
,
-- 8
"
1111011
"
WHEN
"1001"
,
-- 9
"
1
001
00
0"
WHEN
OTHERS
;
-- displays Symbol 'E' for ERROR
"1
00000
0"
WHEN
"0000"
,
-- 0
"
11
1100
1
"
WHEN
"0001"
,
-- 1
"
0100100
"
WHEN
"0010"
,
-- 2
"
0
1100
00
"
WHEN
"0011"
,
-- 3
"
0
011001"
WHEN
"0100"
,
-- 4
"
0010010
"
WHEN
"0101"
,
-- 5
"
0000
01
0
"
WHEN
"0110"
,
-- 6
"111
1
000"
WHEN
"0111"
,
-- 7
"
0000000
"
WHEN
"1000"
,
-- 8
"
0010000
"
WHEN
"1001"
,
-- 9
"
00
001
1
0"
WHEN
OTHERS
;
-- displays Symbol 'E' for ERROR
END
truthtable
;
-------------------------------------------------------------------------------
...
...
src/de1_binto7segment_structure.vhd
0 → 100644
View file @
834fb1c7
LIBRARY
IEEE
;
USE
IEEE
.
std_logic_1164
.
ALL
;
ENTITY
de1_binto7segment
IS
PORT
(
SW
:
IN
std_ulogic_vector
(
3
DOWNTO
0
);
-- Toggle Switch[3:0]
LEDR
:
OUT
std_ulogic_vector
(
3
DOWNTO
0
);
-- LED Red[3:0]
HEX0
:
OUT
std_ulogic_vector
(
6
DOWNTO
0
)
-- Seven Segment Digit 0
);
END
de1_binto7segment
;
ARCHITECTURE
structure
OF
de1_binto7segment
IS
COMPONENT
binto7segment
PORT
(
bin_i
:
IN
std_ulogic_vector
(
3
DOWNTO
0
);
segments_o
:
OUT
std_ulogic_vector
(
6
DOWNTO
0
));
END
COMPONENT
;
BEGIN
-- connecting device under test with peripheral elements
DUT
:
binto7segment
PORT
MAP
(
bin_i
=>
SW
,
segments_o
=>
HEX0
);
-- connect switches to red LEDs
LEDR
<=
SW
;
END
structure
;
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