Commit 8e967938 authored by Friedrich Beckmann's avatar Friedrich Beckmann Committed by Manuel Mikschl
Browse files

add tone generator

I added the tone generator and fixed de1_audio testbench (50 MHz)

The audio codec now works with 50 MHz. I did not change this
in the testbench.
parent 4de75bc9
# Pin Configuration
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY0
set_location_assignment PIN_A3 -to I2C_SCLK
set_location_assignment PIN_B3 -to I2C_SDAT
set_location_assignment PIN_A6 -to AUD_ADCLRCK
set_location_assignment PIN_B6 -to AUD_ADCDAT
set_location_assignment PIN_A5 -to AUD_DACLRCK
set_location_assignment PIN_B5 -to AUD_DACDAT
set_location_assignment PIN_B4 -to AUD_XCK
set_location_assignment PIN_A4 -to AUD_BCLK
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_R17 -to LEDR[9]
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_M1 -to SW[8]
set_location_assignment PIN_L2 -to SW[9]
SIM_PROJECT_NAME = de1_tone
PROJECT = $(SIM_PROJECT_NAME)
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES)
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
include ../makefile
PROJECT = de1_tone
include ./makefile.sources
# Add here the testbench file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/t_$(PROJECT).vhd
include ../makefile
SYN_SOURCE_FILES = \
../../src/adcintf.vhd \
../../src/bclk.vhd \
../../src/dacintf.vhd \
../../src/fsgen.vhd \
../../src/i2c_sub.vhd \
../../src/i2c.vhd \
../../src/i2c_write.vhd \
../../src/mclk.vhd \
../../src/audio.vhd \
../../src/tone_rtl.vhd \
../../src/de1_tone.vhd
--Copyright 2013,2021 Friedrich Beckmann, Hochschule Augsburg
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera;
use altera.altera_primitives_components.all;
entity de1_tone is
port (
CLOCK_50 : in std_ulogic;
KEY0 : in std_ulogic;
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_logic;
AUD_ADCLRCK : out std_ulogic;
AUD_ADCDAT : in std_ulogic;
AUD_DACLRCK : out std_ulogic;
AUD_DACDAT : out std_ulogic;
AUD_XCK : out std_ulogic;
AUD_BCLK : out std_ulogic;
SW : in std_ulogic_vector(9 downto 0);
LEDR : out std_ulogic_vector(9 downto 0));
end;
architecture struct of de1_tone is
component audio is
port (
clk_i : in std_ulogic;
reset_ni : in std_ulogic;
i2c_sclk_o : out std_ulogic;
i2c_dat_i : in std_ulogic;
i2c_dat_o : out std_ulogic;
aud_adclrck_o : out std_ulogic;
aud_adcdat_i : in std_ulogic;
aud_daclrck_o : out std_ulogic;
aud_dacdat_o : out std_ulogic;
aud_xck_o : out std_ulogic;
aud_bclk_o : out std_ulogic;
adc_data_o : out std_ulogic_vector(15 downto 0);
adc_valid_o : out std_ulogic;
dac_data_i : in std_ulogic_vector(15 downto 0);
dac_strobe_o : out std_ulogic);
end component;
component tone is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
switches_i : in std_ulogic_vector(9 downto 0);
dv_i : in std_ulogic;
audio_i : in std_ulogic_vector(15 downto 0);
audio_o : out std_ulogic_vector(15 downto 0));
end component;
signal clk, reset_n : std_ulogic;
signal i2c_dat_o : std_ulogic;
signal i2c_dat_i : std_ulogic;
signal adc_valid : std_ulogic;
signal dac_strobe : std_ulogic;
signal dac_data, adc_data : std_ulogic_vector(15 downto 0);
begin
reset_n <= KEY0;
clk <= CLOCK_50;
audio_i0 : audio
port map (
clk_i => clk,
reset_ni => reset_n,
i2c_sclk_o => I2C_SCLK,
i2c_dat_i => i2c_dat_i,
i2c_dat_o => i2c_dat_o,
aud_adclrck_o => AUD_ADCLRCK,
aud_adcdat_i => AUD_ADCDAT,
aud_daclrck_o => AUD_DACLRCK,
aud_dacdat_o => AUD_DACDAT,
aud_xck_o => AUD_XCK,
aud_bclk_o => AUD_BCLK,
adc_data_o => adc_data,
adc_valid_o => adc_valid,
dac_data_i => dac_data,
dac_strobe_o => dac_strobe);
tone_i0 : tone
port map (
clk => clk,
rst_n => reset_n,
dv_i => adc_valid,
audio_i => adc_data,
audio_o => dac_data,
switches_i => SW);
LEDR(9 downto 0) <= SW;
-- i2c has an open-drain ouput
i2c_dat_i <= I2C_SDAT;
i2c_data_buffer_i : OPNDRN
port map (a_in => i2c_dat_o, a_out => I2C_SDAT);
end; -- architecture
......@@ -12,7 +12,6 @@
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -24,7 +23,7 @@ architecture tbench of t_de1_audio is
component de1_audio is
port (
CLOCK_24: in std_ulogic;
CLOCK_50: in std_ulogic;
KEY0: in std_ulogic;
I2C_SCLK: out std_ulogic;
I2C_SDAT: inout std_ulogic;
......@@ -51,7 +50,7 @@ begin
de1_audio_i0 : de1_audio
port map (
CLOCK_24 => clk,
CLOCK_50 => clk,
KEY0 => reset_n,
I2C_SCLK => i2c_clk,
I2C_SDAT => i2c_dat,
......@@ -66,9 +65,9 @@ begin
clock_p : process
begin
clk <= '0';
wait for 21 ns;
wait for 10 ns;
clk <= '1';
wait for 21 ns;
wait for 10 ns;
if not simrun then
wait;
end if;
......
--Copyright 2013 Friedrich Beckmann, Hochschule Augsburg
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity t_de1_tone is
end;
architecture tbench of t_de1_tone is
component de1_tone is
port (
CLOCK_50 : in std_ulogic;
KEY0 : in std_ulogic;
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_ulogic;
AUD_ADCLRCK : out std_ulogic;
AUD_ADCDAT : in std_ulogic;
AUD_DACLRCK : out std_ulogic;
AUD_DACDAT : out std_ulogic;
AUD_XCK : out std_ulogic;
AUD_BCLK : out std_ulogic;
SW : in std_ulogic_vector(9 downto 0);
LEDR : out std_ulogic_vector(9 downto 0)
);
end component;
signal clk, reset_n : std_ulogic;
signal ledr : std_ulogic_vector(9 downto 0);
signal i2c_clk, i2c_dat : std_ulogic;
signal key0 : std_ulogic;
signal aud_adclrck, aud_adcdat, aud_daclrck, aud_dacdat, aud_xck, aud_bclk : std_ulogic;
signal simrun : boolean := true;
signal phase : real := 0.0;
signal test_tone : real;
signal test_tone_quantized : signed(15 downto 0);
signal bit_count : integer range 0 to 31;
signal switches : std_ulogic_vector(9 downto 0);
begin
de1_tone_i0 : de1_tone
port map (
CLOCK_50 => clk,
KEY0 => reset_n,
I2C_SCLK => i2c_clk,
I2C_SDAT => i2c_dat,
AUD_ADCLRCK => aud_adclrck,
AUD_ADCDAT => aud_adcdat,
AUD_DACLRCK => aud_daclrck,
AUD_DACDAT => aud_dacdat,
AUD_XCK => aud_xck,
AUD_BCLK => aud_bclk,
SW => switches,
LEDR => ledr);
clock_p : process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
if not simrun then
wait;
end if;
end process clock_p;
simrun <= false after 5 ms;
reset_p : process
begin
reset_n <= '0';
wait for 15 us;
reset_n <= '1';
wait;
end process reset_p;
aud_adcdat <= test_tone_quantized(bit_count mod 16);
-- Test tone generator for simulating the ADC from the audio codec
phase <= phase + 1.0/48.0 when rising_edge(aud_daclrck);
test_tone <= sin(2*3.14*phase);
test_tone_quantized <= to_signed(integer(test_tone * real(2**15-1)), 16);
bit_count <= 31 when falling_edge(aud_daclrck) else
0 when bit_count = 0 else
bit_count - 1 when falling_edge(aud_bclk);
end; -- architecture
library ieee;
use ieee.std_logic_1164.all;
entity tone is
port (clk : in std_ulogic;
rst_n : in std_ulogic;
switches_i : in std_ulogic_vector(9 downto 0);
dv_i : in std_ulogic;
audio_i : in std_ulogic_vector(15 downto 0);
audio_o : out std_ulogic_vector(15 downto 0));
end entity;
architecture rtl of tone is
begin
audio_o <= audio_i when rising_edge(clk) and dv_i = '1';
end architecture rtl;
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