lab#6: Extending calculator part 2 (testing)

0001-Added-wrapper-for-basic-calculator.patch

-From dadb3ba23ed70658f686986d2fa670c9c60edac5 Mon Sep 17 00:00:00 2001
-From: Matthias Kamuf <matthias.kamuf@hs-augsburg.de>
-Date: Tue, 6 Apr 2021 14:15:05 +0000
-Subject: [PATCH] Added wrapper for basic calculator
-
----
- src/de1_calculator_structure.vhd | 60 ++++++++++++++++++++++++++++++++
- 1 file changed, 60 insertions(+)
- create mode 100644 src/de1_calculator_structure.vhd
-
-diff --git a/src/de1_calculator_structure.vhd b/src/de1_calculator_structure.vhd
-new file mode 100644
-index 0000000..2def00e
---- /dev/null
-+++ b/src/de1_calculator_structure.vhd
-@@ -0,0 +1,60 @@
-+-------------------------------------------------------------------------------
-+-- Module     : de1_calculator
-+-------------------------------------------------------------------------------
-+-- Author     : Matthias Kamuf
-+-- Company    : University of Applied Sciences Augsburg
-+-------------------------------------------------------------------------------
-+-- Description: Basic calculator for a DE1 prototype board
-+-------------------------------------------------------------------------------
-+-- Revisions  : see end of file
-+-------------------------------------------------------------------------------
-+LIBRARY IEEE;
-+USE IEEE.std_logic_1164.ALL;
-+USE IEEE.numeric_std.ALL;
-+
-+ENTITY de1_calculator IS
-+  PORT (
-+    SW   : IN  std_ulogic_vector(7 DOWNTO 0);  -- Toggle Switch[7:0]
-+    LEDR : OUT std_ulogic_vector(7 DOWNTO 0);  -- LED Red[7:0]
-+    HEX0 : OUT std_ulogic_vector(6 DOWNTO 0)   -- Seven Segment Digit 0
-+    );
-+END de1_calculator;
-+
-+ARCHITECTURE structure OF de1_calculator IS
-+
-+  COMPONENT binto7segment
-+    PORT (
-+      bin_i      : IN  std_ulogic_vector(3 DOWNTO 0);
-+      segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
-+  END COMPONENT;
-+
-+  SIGNAL a   : unsigned(2 DOWNTO 0);
-+  SIGNAL b   : unsigned(2 DOWNTO 0);
-+  SIGNAL sum : unsigned(3 DOWNTO 0);
-+
-+BEGIN
-+
-+  -- connecting switches to operands
-+  -- ...
-+
-+  -- add the operands
-+  -- ...
-+
-+  -- connecting operands to LEDs
-+  LEDR(2 DOWNTO 0) <= SW(2 DOWNTO 0);
-+  LEDR(3)          <= '0';
-+  LEDR(6 DOWNTO 4) <= SW(6 DOWNTO 4);
-+  LEDR(7)          <= '0';
-+
-+  -- display result on HEX0
-+  result_sum : binto7segment
-+    PORT MAP (
-+      bin_i      => std_ulogic_vector(sum),
-+      segments_o => HEX0);
-+
-+END structure;
-+-------------------------------------------------------------------------------
-+-- Revisions:
-+-- ----------
-+-- $Id:$
-+-------------------------------------------------------------------------------
--- 
-2.20.1
-

0004-de1_cntupen_step-KEY1-connected-to-en_pi-of-cntupen.patch

-From 50d52c498fe529687c4b2072f4401fac1b011c06 Mon Sep 17 00:00:00 2001
-From: Johann Faerber <johann.faerber@hs-augsburg.de>
-Date: Tue, 23 Mar 2021 11:13:40 +0100
-Subject: [PATCH] de1_cntupen_step KEY1 connected to en_pi of cntupen
-
----
- src/de1_cntupen_step_structure.vhd | 8 +++-----
- 1 file changed, 3 insertions(+), 5 deletions(-)
-
-diff --git a/src/de1_cntupen_step_structure.vhd b/src/de1_cntupen_step_structure.vhd
-index 8b9f81f..87ebfb8 100644
---- a/src/de1_cntupen_step_structure.vhd
-+++ b/src/de1_cntupen_step_structure.vhd
-@@ -63,15 +63,13 @@ BEGIN
-   -- KEY(1) ist low-active
-   long_pulse <= KEY(1);
- 
--  -- enable signal en_pi has to be connected via a falling edge detector
--  single_pulse_generator : ENTITY work.falling_edge_detector(rtl)
--    PORT MAP (
--
-       
-   -- connecting device under test with peripheral elements
-   DUT : ENTITY work.cntupen(rtl)
-     PORT MAP (
--
-+      clk_i   => clk_i,
-+      rst_ni  => rst_ni,
-+      en_pi   => long_pulse,
-       
-   -- connecting count value to HEX display
-   count_value : ENTITY work.binto7segment(truthtable)
--- 
-2.20.1
-

pnr/de1_heartbeat_gen/de1_heartbeat_gen_pins.tcl

+# assign pin locations to a quartus project
+
+#----------------------------------------------------------------------
+# Pin Assignments
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+
+# ----------------------------------------------------------------------------

pnr/de1_heartbeat_gen/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with Quartus,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# - assign variable SIM_PROJECT_NAME with the top level project name
+# - add additional VHDL sources to SOURCE_FILES, if necessary
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
+###################################################################
+
+SIM_PROJECT_NAME = heartbeat_gen
+PROJECT = de1_$(SIM_PROJECT_NAME)
+
+# Prototype Board FPGA family and device settings
+# DE1
+FAMILY = "Cyclone II"
+DEVICE = EP2C20F484C7
+PROGFILEEXT = sof
+# DEMMK
+# FAMILY = "MAX II"
+# DEVICE = EPM2210F324C3
+# PROGFILEEXT = pof
+# DE2
+#FAMILY = "Cyclone II"
+#DEVICE = EP2C35F484C7
+#PROGFILEEXT = sof
+# DE0
+#FAMILY = "Cyclone IV E"
+#DEVICE = EP4CE22F17C6
+#PROGFILEEXT = sof
+
+# Here the VHDL files for synthesis are defined. 
+include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
+
+# Add the toplevel fpga vhdl file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/$(PROJECT)_rtl.vhd
+
+include ../makefile
+
+

sim/heartbeat_gen/makefile

+## ----------------------------------------------------------------------------
+## Script     : makefile
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber, Friedrich Beckmann
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: This makefile allows automating design flow with ModelSim,
+##              it is based on a design directory structure described in 
+##              ../makefile
+## ----------------------------------------------------------------------------
+
+###################################################################
+# Project Configuration: 
+#
+# assign variable PROJECT with the top level project name
+#
+# Prerequisite: 
+#   - mandatory design directory structure (see end of file)
+#   - assumes file name of testbench t_$(PROJECT).vhd
+###################################################################
+
+PROJECT = heartbeat_gen
+
+include ./makefile.sources
+
+# Add here the testbench file
+SOURCE_FILES = $(SYN_SOURCE_FILES) \
+../../src/t_$(PROJECT).vhd
+
+include ../makefile
+
+## ----------------------------------------------------------------------------
+## Description: 
+## ------------
+## assumes the following design directory structure as prerequisite
+## 
+## DigitaltechnikPraktikum
+## |   
+## +---src
+## |       and2gate_equation.vhd
+## |       invgate_equation.vhd
+## |       mux2to1_structure.vhd
+## |       or2gate_equation.vhd
+## |       t_mux2to1.vhd
+## |       de1_mux2to1_structure.vhd
+## |
+## +---sim
+## |   |   makefile
+## |   |
+## |   \---mux2to1
+## |           makefile
+## |           makefile.sources
+## |
+## +---pnr
+## |   |   makefile
+## |   |
+## |   \---de1_mux2to1
+## |           de1_mux2to1_pins.tcl
+## |           makefile
+## |
+## \---scripts
+##         de1_pin_assignments_minimumio.csv
+##         de1_pin_assignments_minimumio.tcl
+##         modelsim.ini
+##         quartus_project_settings.tcl
+## ----------------------------------------------------------------------------
+

sim/heartbeat_gen/makefile.sources

+## ----------------------------------------------------------------------------
+## Script     : makefile.sources
+## ----------------------------------------------------------------------------
+## Author     : Johann Faerber
+## Company    : University of Applied Sciences Augsburg
+## ----------------------------------------------------------------------------
+## Description: provide all the VHDL source files in the variable SYN_SOURCE_FILES
+##              Attention !!!
+##              -------------
+##              Do not forget a new line after the final source file !
+## ----------------------------------------------------------------------------
+
+SYN_SOURCE_FILES = \
+../../src/heartbeat_gen_rtl.vhd \
+
+# do not delete this line
+# -----------------------------------------------------------------------------

src/#de1_cntupdn_structure.vhd#

+-------------------------------------------------------------------------------
+-- Module     : de1_cntupdn
+-------------------------------------------------------------------------------
+-- Author     : Johann Faerber
+-- Company    : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: test the module cntupdn on a DE1 prototype board
+--              connecting device under test (DUT) cntupdn
+--              to input/output signals of the DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+
+ENTITY de1_cntupdn IS
+  PORT (
+    CLOCK_50 : IN  std_ulogic;                     -- 50 MHz Clock
+    KEY      : IN  std_ulogic_vector(2 DOWNTO 0);  -- KEY[1:0]
+                                                   -- KEY[0] = rst_ni
+                                                   -- KEY[1] = en_pi
+                                                   -- KEY[1] = mode_i
+    GPO_1    : OUT std_ulogic_vector(5 DOWNTO 0)   -- Output Connector GPIO_1
+                                                   -- GPO_1[3:0] = count_o
+                                                   -- GPO_1[4] = mode_i
+                                                   -- GPO_1[5] = clk_i
+    );
+END de1_cntupdn;
+
+ARCHITECTURE structure OF de1_cntupdn IS
+
+  COMPONENT cntupdn IS
+    PORT (
+      clk_i   : IN  std_ulogic;
+      rst_ni  : IN  std_ulogic;
+      en_pi   : IN  std_ulogic;
+      mode_i  : IN  std_ulogic;
+      count_o : OUT std_ulogic_vector(3 DOWNTO 0));
+  END COMPONENT cntupdn;
+  
+  SIGNAL clk_i   : std_ulogic;
+  SIGNAL rst_ni  : std_ulogic;
+  SIGNAL en_pi   : std_ulogic;
+  SIGNAL mode_i  : std_ulogic;
+  SIGNAL count_o : std_ulogic_vector(3 DOWNTO 0);
+  
+BEGIN
+
+  -- connecting clock generator master clock of synchronous system
+
+  
+  -- connecting asynchronous system reset to digital system
+
+  
+  -- count enable input is high-active, KEY(1) ist low-aktive, therefore ...
+
+
+  -- count direction controller by mode_i, connected to KEY(2)
+
+
+  -- connecting device under test with peripheral elements
+
+  
+  -- connecting count value to GPIO1
+
+
+  
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------

src/de1_heartbeat_gen_structure.vhd

+-------------------------------------------------------------------------------
+-- Module     : de1_heartbeat_gen
+-------------------------------------------------------------------------------
+--
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+ENTITY de1_heartbeat_gen IS
+  PORT (
+    KEY0   :  IN  std_ulogic;
+    LEDR   :  OUT std_ulogic_vector(9 DOWNTO 0);
+    );
+END de1_heartbeat_gen;
+
+ARCHITECTURE structure OF de1_heartbeat_gen IS
+
+  COMPONENT cntdnmodm IS
+    PORT (
+      clk_i  : IN  std_ulogic;
+      rst_ni : IN  std_ulogic;
+      en_pi  : IN  std_ulogic;
+      count_o : OUT std_ulogic_vector(?? DOWNTO 0));
+  END COMPONENT cntdnmodm;
+
+  COMPONENT heartbeat_gen IS
+    PORT (
+      clk_i       : IN  std_ulogic;
+      rst_ni      : IN  std_ulogic;
+      en_pi       : IN  std_ulogic;
+      cout_o      : OUT std_ulogic_vector(?? DOWNTO 0);
+      heartbeat_o : OUT std_ulogic);
+  END COMPONENT heartbeat_gen;
+
+  
+      

src/heartbeat_gen_rtl.vhd

+-------------------------------------------------------------------------------
+-- Module     : heartbeat_gen_rtl
+-------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Revisions  : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+ENTITY heartbeat_gen IS
+  PORT (clk_i       : IN  std_ulogic;
+        rst_ni      : IN  std_ulogic;
+        en_pi       : IN  std_ulogic;
+        count_o     : OUT std_ulogic_vector(n-1 DOWNTO 0);
+        heartbeat_o : OUT std_ulogic
+        );
+END heartbeat_gen;
+
+ARCHITECTURE rtl OF heartbeat_gen IS
+
+
+
+BEGIN
+
+
+
+
+END rtl;

src/t_heartbeat_gen.vhd

+-- tbench heartbeat gen