Commit 9a555374 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab6: basic calculator finished

parent 4a0f9340
From dadb3ba23ed70658f686986d2fa670c9c60edac5 Mon Sep 17 00:00:00 2001
From: Matthias Kamuf <matthias.kamuf@hs-augsburg.de>
Date: Tue, 6 Apr 2021 14:15:05 +0000
Subject: [PATCH] Added wrapper for basic calculator
---
src/de1_calculator_structure.vhd | 60 ++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 src/de1_calculator_structure.vhd
diff --git a/src/de1_calculator_structure.vhd b/src/de1_calculator_structure.vhd
new file mode 100644
index 0000000..2def00e
--- /dev/null
+++ b/src/de1_calculator_structure.vhd
@@ -0,0 +1,60 @@
+-------------------------------------------------------------------------------
+-- Module : de1_calculator
+-------------------------------------------------------------------------------
+-- Author : Matthias Kamuf
+-- Company : University of Applied Sciences Augsburg
+-------------------------------------------------------------------------------
+-- Description: Basic calculator for a DE1 prototype board
+-------------------------------------------------------------------------------
+-- Revisions : see end of file
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+ENTITY de1_calculator IS
+ PORT (
+ SW : IN std_ulogic_vector(7 DOWNTO 0); -- Toggle Switch[7:0]
+ LEDR : OUT std_ulogic_vector(7 DOWNTO 0); -- LED Red[7:0]
+ HEX0 : OUT std_ulogic_vector(6 DOWNTO 0) -- Seven Segment Digit 0
+ );
+END de1_calculator;
+
+ARCHITECTURE structure OF de1_calculator IS
+
+ COMPONENT binto7segment
+ PORT (
+ bin_i : IN std_ulogic_vector(3 DOWNTO 0);
+ segments_o : OUT std_ulogic_vector(6 DOWNTO 0));
+ END COMPONENT;
+
+ SIGNAL a : unsigned(2 DOWNTO 0);
+ SIGNAL b : unsigned(2 DOWNTO 0);
+ SIGNAL sum : unsigned(3 DOWNTO 0);
+
+BEGIN
+
+ -- connecting switches to operands
+ -- ...
+
+ -- add the operands
+ -- ...
+
+ -- connecting operands to LEDs
+ LEDR(2 DOWNTO 0) <= SW(2 DOWNTO 0);
+ LEDR(3) <= '0';
+ LEDR(6 DOWNTO 4) <= SW(6 DOWNTO 4);
+ LEDR(7) <= '0';
+
+ -- display result on HEX0
+ result_sum : binto7segment
+ PORT MAP (
+ bin_i => std_ulogic_vector(sum),
+ segments_o => HEX0);
+
+END structure;
+-------------------------------------------------------------------------------
+-- Revisions:
+-- ----------
+-- $Id:$
+-------------------------------------------------------------------------------
--
2.20.1
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
# ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = calculator
PROJECT = de1_$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
# DEMMK
# FAMILY = "MAX II"
# DEVICE = EPM2210F324C3
# PROGFILEEXT = pof
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
#PROGFILEEXT = sof
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
#PROGFILEEXT = sof
# Here the VHDL files for synthesis are defined.
#include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = ../../src/$(PROJECT)_structure.vhd \
../../src/de1_binto7segment_structure.vhd \
../../src/binto7segment_truthtable.vhd
include ../makefile
......@@ -35,10 +35,11 @@ ARCHITECTURE structure OF de1_calculator IS
BEGIN
-- connecting switches to operands
-- ...
a <= unsigned(SW(2 DOWNTO 0));
b <= unsigned(SW(6 DOWNTO 4));
-- add the operands
-- ...
sum <= resize(a, sum'length) + resize(b, sum'length);
-- connecting operands to LEDs
LEDR(2 DOWNTO 0) <= SW(2 DOWNTO 0);
......
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