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Commit a1401c27 authored by Oran Garrity's avatar Oran Garrity
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Lab#10 Game

parent e71ca919
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src/Game Description 0 → 100644
View file @ a1401c27
LEDs count down from 5-1, then will reset when when the key is not pressed and reaches 1.
If the key is pressed only chance_s then the system will go to hit0_s. When the key is pressed in this state in a second it will revert back to the chance_s, if not the system will go to hit1_s after a second. This will loop if the key is not pressed. If the key is pressed then the system will go back to the chance_s state.
\ No newline at end of file
src/Lab10_idea.fsm
View file @ a1401c27
......@@ -8,14 +8,14 @@
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......@@ -27,7 +27,7 @@
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......
src/a_falling_edge_detector_fsm.vhd
View file @ a1401c27
library IEEE;
use IEEE.std_logic_1164.all;
architecture fsm of falling_edge_detector is
signal q0,q1 : std_ulogic;
architecture rtl of falling_edge_detector is
TYPE state_t IS (state_0, state_1, state_2);
signal current_state, new_state : state_t;
begin
process(current_state, x_i)
BEGIN
new_state <= state_0;
fall_o <= '0';
CASE current_state IS
WHEN state_0 =>
IF x_i = '1' THEN new_state <= state_1; END if;
WHEN state_1 =>
IF x_i = '0' THEN new_state <= state_2;
ELSIF x_i = '1' THEN new_state <= state_1; END if;
q0 <= '1' when rst_ni = '0' else x_i when rising_edge(clk_i);
q1 <= '1' when rst_ni = '0' else q0 when rising_edge(clk_i);
fall_o <= '1' when q1 = '1' and q0 = '0' else '0';
WHEN state_2 =>
fall_o <= '1';
WHEN OTHERS => new_state <= state_0;
END case;
END process;
current_state <= state_0 WHEN rst_ni = '0' ELSE
new_state WHEN rising_edge(clk_i);
end architecture;
src/lab10_game.fsm 0 → 100644
View file @ a1401c27
<?xml version='1.0'?>
<!DOCTYPE qfsmproject SYSTEM 'qfsm.dtd'>
<qfsmproject version="0.55" author="Qfsm">
<machine nummooreout="5" transfontitalic="0" draw_it="1" statefontsize="8" transfont="Helvetica" statefontitalic="0" author="" description="" version="" name="play_state" arrowtype="1" numbits="3" statefontweight="50" statefont="Helvetica" numin="2" transfontsize="8" transfontweight="50" type="0" numout="0" initialstate="0">
<outputnames_moore>led_o_0,led_o_1,led_o_2,led_o_3,led_o_4</outputnames_moore>
<inputnames>key_i,onesec_i</inputnames>
<outputnames></outputnames>
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src/t_de1_play.vhd
View file @ a1401c27
......@@ -27,11 +27,14 @@ end component;
-- definition of a clock period
constant period : time := 10 ns;
constant onesec : time := 20 ns;
-- switch for clock generator
signal clken_p : boolean := true;
signal clk_i : std_ulogic;
signal onesec_i : std_ulogic;
signal rst_ni : std_ulogic;
signal key : std_ulogic;
signal ledr : std_ulogic_vector(4 downto 0);
......@@ -55,6 +58,15 @@ begin
wait;
end process;
onesec_proc : process
begin
while clken_p loop
onesec_i <= '0'; wait for onesec/2;
onesec_i <= '1'; wait for onesec/2;
end loop;
wait;
end process;
-- initial reset, always necessary at the beginning of a simulation
reset : rst_ni <= '0', '1' AFTER period;
......
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