Commit ac75dcdb authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

bugfix: t_de1_play, count1s_rtl and falling_edge_detector (state machine)

parent 1d9fa5b5
......@@ -2,31 +2,37 @@ library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of falling_edge_detector is
TYPE state_t IS (state_0, state_1, state_2);
TYPE state_t IS (state0_s, state1_s, state2_s);
signal current_state, new_state : state_t;
begin
process(current_state, x_i)
BEGIN
-- new state and output logic
sm_p : process(current_state, x_i)
BEGIN
new_state <= state_0;
fall_o <= '0';
-- default arguments
new_state <= current_state;
fall_o <= '0';
CASE current_state IS
WHEN state_0 =>
IF x_i = '1' THEN new_state <= state_1; END if;
WHEN state0_s =>
IF x_i = '1' THEN new_state <= state1_s; END if;
WHEN state_1 =>
IF x_i = '0' THEN new_state <= state_2;
ELSIF x_i = '1' THEN new_state <= state_1; END if;
WHEN state1_s =>
IF x_i = '0' THEN new_state <= state2_s; END if;
WHEN state_2 =>
WHEN state2_s =>
new_state <= state0_s;
fall_o <= '1';
WHEN OTHERS => new_state <= state_0;
WHEN OTHERS => new_state <= state0_s;
END case;
END process;
current_state <= state_0 WHEN rst_ni = '0' ELSE
current_state <= state0_s WHEN rst_ni = '0' ELSE
new_state WHEN rising_edge(clk_i);
end architecture;
......@@ -6,8 +6,8 @@ entity count1s is
GENERIC(
n : natural := 26;
m : natural := 50000000);
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
port ( clk : in std_ulogic;
rst_n : in std_ulogic;
onesec_o : out std_ulogic);
end entity;
......
......@@ -10,8 +10,8 @@ architecture tbench of t_de1_play is
component de1_play is
port (
CLOCK_50 : in std_ulogic; -- 50 mhz clock
KEY : in std_ulogic_vector(1 downto 0); -- key(1..0)
CLOCK_50 : in std_ulogic; -- 50 mhz clock
KEY : in std_ulogic_vector(1 downto 0); -- key(1..0)
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_logic;
SW : in std_ulogic_vector(9 downto 0);
......@@ -21,14 +21,13 @@ component de1_play is
AUD_DACDAT : out std_ulogic;
AUD_XCK : out std_ulogic;
AUD_BCLK : out std_ulogic;
LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0)
LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0)
LEDR : out std_ulogic_vector(4 downto 0); -- red LED(4..0)
LEDG : out std_ulogic_vector(1 downto 0) -- green LED(1..0)
);
end component;
-- definition of a clock period
constant period : time := 10 ns;
constant onesec : time := 20 ns;
-- switch for clock generator
signal clken_p : boolean := true;
......@@ -62,15 +61,6 @@ begin
wait;
end process;
onesec_proc : process
begin
while clken_p loop
onesec_i <= '0'; wait for onesec/2;
onesec_i <= '1'; wait for onesec/2;
end loop;
wait;
end process;
-- initial reset, always necessary at the beginning of a simulation
reset : rst_ni <= '0', '1' AFTER period;
......@@ -94,9 +84,9 @@ begin
de1_play_i0 : de1_play
port map (
CLOCK_50 => clk_i,
KEY(0) => rst_ni,
KEY(1) => key,
CLOCK_50 => clk_i,
KEY(0) => rst_ni,
KEY(1) => key,
I2C_SCLK => i2c_clk,
SW => switches,
I2C_SDAT => i2c_dat,
......
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