Commit b3a2753b authored by Oran Garrity's avatar Oran Garrity
Browse files

Increasing Delay value in Matlab Audio File

parent 7b40816f
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/audio_first/ml_audio.vhd
-- Created: 2021-03-31 10:46:30
-- Created: 2021-03-31 11:14:10
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
......@@ -62,7 +62,7 @@ ARCHITECTURE rtl OF ml_audio IS
SIGNAL Product_mul_temp : signed(26 DOWNTO 0); -- sfix27_En25
SIGNAL Product_cast_1 : signed(25 DOWNTO 0); -- sfix26_En25
SIGNAL Product_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay1_reg : vector_of_signed16(0 TO 9); -- sfix16 [10]
SIGNAL Delay1_reg : vector_of_signed16(0 TO 19); -- sfix16 [20]
SIGNAL Delay1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
BEGIN
......@@ -96,12 +96,12 @@ BEGIN
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay1_reg(0) <= Product_out1;
Delay1_reg(1 TO 9) <= Delay1_reg(0 TO 8);
Delay1_reg(1 TO 19) <= Delay1_reg(0 TO 18);
END IF;
END IF;
END PROCESS Delay1_process;
Delay1_out1 <= Delay1_reg(9);
Delay1_out1 <= Delay1_reg(19);
audio_o <= std_logic_vector(Delay1_out1);
......
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/audio_first/ml_audio_pkg.vhd
-- Created: 2021-03-31 10:46:30
-- Created: 2021-03-31 11:14:10
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
......
......@@ -48,7 +48,7 @@
<div class="page_container"><div class="content_frame">
<h1>HDL Code Generation Check Report for 'audio_first/ml_audio'
<a href="matlab:open_system('audio_first/ml_audio');">open model 'audio_first/ml_audio'</a><BR>
Generated on 2021-03-31 10:46:31</h1>
Generated on 2021-03-31 11:14:12</h1>
<H2>No messages, warnings, or errors were found.</H2><BR>
<BR><BR> </div></div></div></div>
<div class="grid_192">
......
<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"/><title>Model Advisor Report Customization</title>
<style>
H3 {font-size:14pt; font-weight:200;}
H4 {font-size:9pt; font-weight:normal;}
</style>
</head>
<body>
<H3 align="center">Model Advisor Customization </H3>
<p align="right"><a href="matlab: modeladvisor 'help'"><b>Help</b></a></p>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check rapid accelerator signal logging</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckRapidAcceleratorSignalLogging</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify Model Variants blocks and convert those to Variant Subsystem blocks containing Model block choices</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ConvertMdlrefVarToVSS</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check get_param calls for block CompiledSampleTime</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CallsGetParamCompiledSampleTime</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify unconnected lines, input ports, and output ports</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.UnconnectedLinesPorts</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check root model Inport block specifications</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.RootInportSpec</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check diagnostic settings ignored during accelerated model reference simulation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ModelRefSIMConfigCompliance</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for parameter tunability information ignored for referenced models</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ParamTunabilityIgnored</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for implicit signal resolution</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ImplicitSignalResolution</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for optimal bus virtuality</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.OptBusVirtuality</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for calls to slDataTypeAndScale()</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CallslDataTypeAndScale</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Discrete-Time Integrator blocks with initial condition uncertainty</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DiscreteTimeIntegratorInitCondition</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify disabled library links</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DisabledLibLinks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify parameterized library links</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ParameterizedLibLinks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify unresolved library links</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.UnresolvedLibLinks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify configurable subsystem template blocks having the instances in the model for converting to variant subsystem blocks.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CSStoVSSConvert</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check usage of function-call connections</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckForProperFcnCallUsage</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check and update masked blocks in library to use promoted parameters</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckAndUpdateOldMaskedBuiltinBlocks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check and update mask image display commands with unnecessary imread() function calls</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckMaskDisplayImageFormat</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check and update mask to affirm icon drawing commands dependency on mask workspace</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckMaskRunInitFlag</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td></td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.hdlssc.ssccodegenadvisor.workflowObjectCheck</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Extract equations</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.hdlssc.ssccodegenadvisor.getStateSpaceParametersTask</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set Target Frequency</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetGenericTargetFrequency</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set Target Frequency</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetFrequency</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model-level settings for HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckGlobalSettings</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set basic options for RTL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetBasicOptions</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set report options</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetReportOptions</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set advanced options</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetAdvancedOptions</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set Optimization Options</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetOptimizationOptions</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set testbench options</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTBOptions</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Verify generated RTL code with a HDL Cosimulation testbench</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.VerifyCosim</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Create synthesis tool project</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CreateProject</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Run logic synthesis for specified FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.RunLogicSynthesis</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Run mapping for specified FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.RunMapping</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Run place and route for specified FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.RunPandR</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Run logic synthesis for specified FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.RunVivadoSynthesis</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Run place and route for specified FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.RunImplementation</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Annotate synthesis result back to the Simulink model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.AnnotateModel</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate programming file for specified FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.GenerateBitstream</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Program target FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ProgramDevice</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate Simulink Real-Time interface</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.GeneratexPCInterface</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set FPGA-in-the-Loop Options</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.FILOption</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate FPGA programming file and FPGA-in-the-Loop testbench model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.RunFIL</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate FPGA programming file for USRP(R) board. The FPGA project is generated first. Then syntax checking is performed on the HDL code. If no error was found in FPGA project generation and syntax checking, FPGA programming file generation process will start in an external command-line window.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.RunUSRP</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Create project for embedded system tool</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.EmbeddedProject</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate a software interface for the IP core</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.EmbeddedModelGen</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate a software interface model with IP core driver blocks.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.EmbeddedCustomModelGen</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Synthesis and generate bitstream for embedded system on FPGA</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.EmbeddedSystemBuild</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Program target FPGA device</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.EmbeddedDownload</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runBlockSupportChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for MATLAB Function block settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runMLFcnBlkChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for obsolete Unit Delay Enabled/Resettable blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runObsoleteDelaysChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for infinite and continuous sample time sources</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runSampleTimeChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported storage class for signal objects</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runSignalObjectStorageClassChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Stateflow chart settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runStateflowChartSettingsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check architecture name</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runArchitectureNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check clock settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runClockChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check clock, reset, and enable signals</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runClockResetEnableChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check VHDL file extension</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runFileExtensionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check generics</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runGenericChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check naming conventions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNameConventionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check package file names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runPackageNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check signal and port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runPortSignalNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check entity and architecture</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runSplitEntityArchitectureChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check module/entity names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runSubsystemNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check top-level subsystem/port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runToplevelNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check delay balancing setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runBalanceDelaysChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for global reset setting for Xilinx and Altera devices</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runGlobalResetChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check inline configurations setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runInlineConfigurationsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for model parameters suited for the HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runModelParamsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for visualization settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runVisualizationChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check blocks with nonzero ulp error</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPULPErrorChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check initial conditions of enabled and triggered subsystems</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runEnTrigInitConChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for invalid top level subsystem</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runInvalidDUTChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runBlockSupportChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for MATLAB Function block settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runMLFcnBlkChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for obsolete Unit Delay Enabled/Resettable blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runObsoleteDelaysChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for infinite and continuous sample time sources</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSampleTimeChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported storage class for signal objects</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSignalObjectStorageClassChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Stateflow chart settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runStateflowChartSettingsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runDisabledLibLinks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runDisabledLibLinks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runReplaceZOHDelayByRTB</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runReplaceZOHDelayByRTB</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runUnconnectedLinesPorts</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runUnconnectedLinesPorts</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runUnresolvedLibLinks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runUnresolvedLibLinks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check architecture name</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runArchitectureNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check clock settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runClockChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check clock, reset, and enable signals</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runClockResetEnableChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check VHDL file extension</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runFileExtensionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check generics</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runGenericChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check naming conventions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNameConventionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check package file names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runPackageNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check signal and port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runPortSignalNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check entity and architecture</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSplitEntityArchitectureChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check module/entity names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSubsystemNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check top-level subsystem/port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runToplevelNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check delay balancing setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runBalanceDelaysChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for global reset setting for Xilinx and Altera devices</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runGlobalResetChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check inline configurations setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runInlineConfigurationsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for model parameters suited for the HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runModelParamsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for visualization settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runVisualizationChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runCharacterEncoding</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runCharacterEncoding</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check blocks with nonzero ulp error</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPULPErrorChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check initial conditions of enabled and triggered subsystems</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runEnTrigInitConChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for invalid top level subsystem</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runInvalidDUTChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Runtime diagnostics for S-functions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DiagnosticSFcn</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check if Read/Write diagnostics are enabled for Data Store blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DiagnosticDataStoreBlk</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check Data Store Memory blocks for multitasking, strong typing, and shadowing issues</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DataStoreMemoryBlkIssue</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check that the model is saved in SLX format</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.UseSLXFile</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for foreign characters</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.characterEncoding</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check Model History properties</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.SLXModelProperties</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify masked blocks that specify tabs in mask dialog using MaskTabNames parameter</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckAndUpdateOldMaskTabnames</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check conversion input parameters</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.InputParameters</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model configurations</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.ModelConfigurations</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check subsystem interface</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemInterface</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check subsystem content</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemContent</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Complete conversion</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.CompleteConversion</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify variant blocks using variant objects with empty conditions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.emptyVariantObject</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify Model Info blocks that can interact with external source control tools</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ModelInfoKeywordSubstitution</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model and local libraries for SB2SL blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.simulink.SB2SL.Check</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify similar library clones and replace them with links to library blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.CloneDetection.IdentifyStructLibraryClones</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify similar graphical clones and replace them with links to library blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.CloneDetection.IdentifyStructGraphicalClones</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify system constants for use in variant transformation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.IdentifyVariantConstant</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify blocks that qualify for variant transformation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.IdentifyVariantCandidate</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Convert blocks to variants</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.VariantTransform</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Step1. Select data store blocks you want to eliminate</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.DSMElim</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Lookup Table Transformation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.LutXform</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check S-functions in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.SFuncAnalyzer</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Open the Upgrade Advisor</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.UpgradeAdvisor.MAEntryPoint</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Upgrade models in a hierarchy</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.UpgradeAdvisor.UpgradeModelHierarchy</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for block upgrade issues</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.Update</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for case mismatches in references to models and libraries</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CaseSensitiveBlockDiagramNames</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Resave in current version of Simulink</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckSavedInCurrentVersion</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Return all simulation outputs as a single Simulink.SimulationOutput object</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckSingleSimulationOutput</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Create baseline to measure the performance. The baseline contains the time to run the simulation and the simulation results (signals logged). To create a baseline, configure the model to log states in the workspace and save the signals in 'Structure with time' format.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CreateBaseline</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Some diagnostics, such as 'Solver data inconsistency', incur run-time overhead during simulation. To improve simulation speed, disable these diagnostics if they are not necessary.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyExpensiveDiagnostics</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Some optimizations, such as 'Block reduction', may be disabled. To improve simulation speed, enable these optimization settings.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyApplicableOptimizations</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Improperly configured lookup table blocks can affect the simulation speed of a model.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.InefficientLookupTableBlocks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Analyze MATLAB System block for code generation capability.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.DetectIntSysObjBlocks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Avoid using Interpreted MATLAB Function blocks.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.DetectIntMATLABFcnBlocks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Disabling simulation target settings, such as 'Echo expressions without semicolons', can improve simulation speed.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckSimTargetEchoStatus</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check if model reference rebuild setting is set to the proper value</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefRebuildSetting</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Opened and uncommented Scopes can impact simulation performance. This check identifies Scope block, Floating Scope block, and Scope Viewer. Scope Viewer does not support commenting out.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyScopes</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify active instrumentation settings on the model. This setting can cause slow simulations due to range collection.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyActiveMMO</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for virtual bus across model reference boundaries</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckVirtualBusAcrossModelReference</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for parameter initialization and tuning issues</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ParameterTuning</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check structure parameter usage with bus signals</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.MismatchedBusParams</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for large number of function arguments from virtual bus across model reference boundary</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckVirtualBusAcrossModelReferenceArgs</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set Target Device and Synthesis Tool for HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetDevice</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set target reference design options</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetReferenceDesign</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set target interface for HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetInterface</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set target interface for HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetInterfaceAndMode</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for algebraic loops</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckAlgebraicLoop</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for unsupported blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckBlockCompatibility</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for global sample time settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckSampleTime</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model compatibility with FPGA-in-the-Loop</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckFIL</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model compatibility with USRP(R) workflow</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckUSRP</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate RTL code and testbench for the selected subsystem</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.GenerateHDLCodeAndReport</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate RTL code and IP core for embedded system</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.GenerateIPCore</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate RTL code and top level wrapper for the selected subsystem</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.GenerateRTLCode</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify similar functional clones and replace them with links to library blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.CloneDetection.IdentifyStructFunctionalClones</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check relative execution orders for Data Store Read and Data Store Write blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.sorting.datastorecheck</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for relative execution order change for Data Store Read and Data Store Write blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.sorting.datastoresimrtwcmp</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check if model with referenced models can be built in parallel with optimal settings.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefParallelBuild</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Use circular buffer to improve simulation speed for Delay blocks with large states.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckDelayBlockCircularBufferSetting</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Simulation might slow down if all these conditions exist: (1) the model is using a variable step solver, (2) the model contains both continuous and discrete rates, and (3) the fastest discrete rate that does not impact continuous integration is relatively smaller than 'Max step size' determined by the solver. Setting 'DecoupledContinuousIntegration' parameter to 'on' might speed up simulation.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckIfNeedDecoupleContDiscRates</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Simulation might slow down if all these conditions exist: (1) the model is using a variable step solver, (2) the model contains blocks having zero-crossings and continuous states, and (3) some zero-crossings are not impacting continuous integration. Setting 'MinimalZcImpactIntegration' parameter to 'on' might speed up simulation.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckIfNeedOptimalSolverResetCausedByZc</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check discrete signals driving derivative port</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckDiscDriveContSignal</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>The selection of an explicit or implicit solver depends on the approximation of the model stiffness at the beginning of the simulation. If the model represents a stiff system, use the ode15s solver. Otherwise, use the ode45 solver.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.SolverTypeSelection</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Adjust co-simulation settings for better performance and accuracy.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckMultiThreadCoSimSetting</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify co-simulation signals that may need explicit numerical compensation.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckNumericCompensationCoSimSetting</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Adjust dataflow domain settings for better performance.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckDataflow</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Changing simulation mode can improve simulation speed.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationModesComparison</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Running with compiler optimizations turned on can improve simulation speed.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationCompilerOptimization</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Validate the overall performance improvement in your model using this check. If performance is worse than baseline, Performance Advisor discards all changes and loads the original model.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.FinalValidation</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check Delay, Unit Delay and Zero-Order Hold blocks for rate transition</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ReplaceZOHDelayByRTB</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check bus signals treated as vectors</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.BusTreatedAsVector</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for potentially delayed function-call block return values</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DelayedFcnCallSubsys</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify block output signals with continuous sample time and non-floating point data type</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.OutputSignalSampleTime</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check usage of Merge blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.MergeBlkUsage</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check usage of Outport blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.InitParamOutportMergeBlk</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check usage of Discrete-Time Integrator blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DiscreteBlock</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model settings for migration to simplified initialization mode</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ModelLevelMessages</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for custom library blocks that rely on frame status of the signal</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DSPFrameUpgrade</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check solver configuration</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.hdlssc.ssccodegenadvisor.checkSolverConfigurationTask</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check switched linear</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.hdlssc.ssccodegenadvisor.checkSwitchedLinearTask</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Discretize equations</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.hdlssc.ssccodegenadvisor.discretizeTask</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Generate implementation model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.hdlssc.ssccodegenadvisor.generateImplementationModelTask</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for large matrix operations</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runMatrixSizesChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for blocks that have nonzero output latency</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPLatencyChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check algebraic loops</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runAlgebraicLoopChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for double datatypes in the model with Native Floating Point</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runDoubleDatatypeChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Data Type Conversion blocks with incompatible settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPDTCChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for HDL Reciprocal block usage</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPHDLRecipChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Relational Operator block usage</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPRelopChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for single datatypes in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPSuggestionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported blocks with Native Floating Point</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPSupportedBlocksChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for large matrix operations</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runMatrixSizesChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for blocks that have nonzero output latency</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPLatencyChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check algebraic loops</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runAlgebraicLoopChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for double datatypes in the model with Native Floating Point</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runDoubleDatatypeChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Data Type Conversion blocks with incompatible settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPDTCChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for HDL Reciprocal block usage</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPHDLRecipChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Relational Operator block usage</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPRelopChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for single datatypes in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPSuggestionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported blocks with Native Floating Point</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPSupportedBlocksChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for non-continuous signals driving derivative ports</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.NonContSigDerivPort</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check data store block sample times for modeling errors</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DataStoreBlkSampleTime</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for potential ordering issues involving data store access</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.OrderingDataStoreAccess</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check virtual bus inputs to blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.VirtualBusUsage</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for root outports with constant sample time</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckConstRootOutportWithInterfaceUpgrade</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for S-function upgrade issues</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckForSFcnUpgradeIssues</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify unit mismatches in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.UnitMismatches</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify automatic unit conversions in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.AutoUnitConversions</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify disallowed unit systems in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DisallowedUnitSystems</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify undefined units in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.UndefinedUnits</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify ambiguous units in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.AmbiguousUnits</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for block upgrade issues requiring compile time information</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.UpdateRequireCompile</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify questionable operations for strict single-precision design</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.StowawayDoubles</td></tr>
<tr><td height="20"></td></tr>
<tr><td height="20"> </td><td> </td></tr>