Commit bd0eb2c4 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

COM: audio_first_sin modified

parent 728570b0
--> ml_audio_pkg
audio_first/ml_audio --> ml_audio
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-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/audio_first/ml_audio.vhd
-- Created: 2021-03-31 11:14:10
-- File Name: hdl_prj/hdlsrc/audio_first_sin/ml_audio.vhd
-- Created: 2021-04-14 10:22:39
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
......@@ -30,14 +30,13 @@
-- -------------------------------------------------------------
--
-- Module: ml_audio
-- Source Path: audio_first/ml_audio
-- Source Path: audio_first_sin/ml_audio
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ml_audio_pkg.ALL;
ENTITY ml_audio IS
PORT( clk : IN std_logic;
......@@ -53,23 +52,62 @@ END ml_audio;
ARCHITECTURE rtl OF ml_audio IS
-- Component Declarations
COMPONENT Sine_HDL_Optimized
PORT( u : IN std_logic_vector(15 DOWNTO 0); -- ufix16_En16
x : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Sine_HDL_Optimized
USE ENTITY work.Sine_HDL_Optimized(rtl);
-- Signals
SIGNAL enb : std_logic;
SIGNAL audio_i_signed : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL switches_i_unsigned : unsigned(9 DOWNTO 0); -- ufix10_En10
SIGNAL Product_cast : signed(10 DOWNTO 0); -- sfix11_En10
SIGNAL Product_mul_temp : signed(26 DOWNTO 0); -- sfix27_En25
SIGNAL Product_cast_1 : signed(25 DOWNTO 0); -- sfix26_En25
SIGNAL Product_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay1_reg : vector_of_signed16(0 TO 19); -- sfix16 [20]
SIGNAL Delay1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Data_Type_Conversion_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL Delay2_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL Sum_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL Delay_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Gain_cast : signed(31 DOWNTO 0); -- sfix32_En30
SIGNAL Gain_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Sine : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Sine_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Gain1_cast : signed(31 DOWNTO 0); -- sfix32_En29
SIGNAL Gain1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Sum1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay3_out1 : signed(15 DOWNTO 0); -- sfix16_En15
BEGIN
u_Sine_HDL_Optimized : Sine_HDL_Optimized
PORT MAP( u => std_logic_vector(Delay2_out1), -- ufix16_En16
x => Sine -- sfix16_En14
);
audio_i_signed <= signed(audio_i);
enb <= clk_enable;
switches_i_unsigned <= unsigned(switches_i);
Data_Type_Conversion_out1 <= switches_i_unsigned & '0' & '0' & '0' & '0' & '0' & '0';
Sum_out1 <= Data_Type_Conversion_out1 + Delay2_out1;
Delay2_process : PROCESS (clk, rst_n)
BEGIN
IF rst_n = '0' THEN
Delay2_out1 <= to_unsigned(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay2_out1 <= Sum_out1;
END IF;
END IF;
END PROCESS Delay2_process;
Delay_process : PROCESS (clk, rst_n)
BEGIN
IF rst_n = '0' THEN
......@@ -82,28 +120,29 @@ BEGIN
END PROCESS Delay_process;
switches_i_unsigned <= unsigned(switches_i);
Gain_cast <= resize(Delay_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 32);
Gain_out1 <= Gain_cast(30 DOWNTO 15);
Sine_signed <= signed(Sine);
Gain1_cast <= resize(Sine_signed & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 32);
Gain1_out1 <= Gain1_cast(29 DOWNTO 14);
Product_cast <= signed(resize(switches_i_unsigned, 11));
Product_mul_temp <= Delay_out1 * Product_cast;
Product_cast_1 <= Product_mul_temp(25 DOWNTO 0);
Product_out1 <= Product_cast_1(25 DOWNTO 10);
Sum1_out1 <= Gain_out1 + Gain1_out1;
Delay1_process : PROCESS (clk, rst_n)
Delay3_process : PROCESS (clk, rst_n)
BEGIN
IF rst_n = '0' THEN
Delay1_reg <= (OTHERS => to_signed(16#0000#, 16));
Delay3_out1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay1_reg(0) <= Product_out1;
Delay1_reg(1 TO 19) <= Delay1_reg(0 TO 18);
Delay3_out1 <= Sum1_out1;
END IF;
END IF;
END PROCESS Delay1_process;
END PROCESS Delay3_process;
Delay1_out1 <= Delay1_reg(19);
audio_o <= std_logic_vector(Delay1_out1);
audio_o <= std_logic_vector(Delay3_out1);
ce_out <= clk_enable;
......
--> ml_audio_pkg
audio_first_sin/ml_audio/Sine HDL Optimized --> Sine_HDL_Optimized
audio_first_sin/ml_audio --> ml_audio
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/audio_first/ml_audio_pkg.vhd
-- Created: 2021-03-31 11:14:10
-- File Name: hdl_prj/hdlsrc/audio_first_sin/ml_audio_pkg.vhd
-- Created: 2021-04-14 10:22:39
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
......@@ -14,5 +14,6 @@ USE IEEE.numeric_std.ALL;
PACKAGE ml_audio_pkg IS
TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0);
TYPE vector_of_unsigned18 IS ARRAY (NATURAL RANGE <>) OF unsigned(17 DOWNTO 0);
END ml_audio_pkg;
<!DOCTYPE HTML>
<html xmlns="http://www.w3.org/1999/xhtml" itemscope itemtype="https://www.mathworks.com/help/schema/MathWorksDocPage">
<head>
<title>HDL Check Report for 'audio_first/ml_audio'</title>
<title>HDL Check Report for 'audio_first_sin/ml_audio'</title>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
<script type="text/javascript" src="file:///opt/MATLAB/R2020b/toolbox/hdlcoder/hdlcommon/js_css/jquery-1.7.1.js"></script>
......@@ -46,9 +46,9 @@
<div class="container_192">
<div class="grid_192">
<div class="page_container"><div class="content_frame">
<h1>HDL Code Generation Check Report for 'audio_first/ml_audio'
<a href="matlab:open_system('audio_first/ml_audio');">open model 'audio_first/ml_audio'</a><BR>
Generated on 2021-03-31 11:14:12</h1>
<h1>HDL Code Generation Check Report for 'audio_first_sin/ml_audio'
<a href="matlab:open_system('audio_first_sin/ml_audio');">open model 'audio_first_sin/ml_audio'</a><BR>
Generated on 2021-04-14 10:22:40</h1>
<H2>No messages, warnings, or errors were found.</H2><BR>
<BR><BR> </div></div></div></div>
<div class="grid_192">
......
<html> <head> <meta http-equiv="Content-Type" content="text/html; charset=utf-8"/><title>Model Advisor Report Customization</title>
<style>
H3 {font-size:14pt; font-weight:200;}
H4 {font-size:9pt; font-weight:normal;}
</style>
</head>
<body>
<H3 align="center">Model Advisor Customization </H3>
<p align="right"><a href="matlab: modeladvisor 'help'"><b>Help</b></a></p>
<table cellpadding=0 cellspacing=0 border=0>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
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<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check clock, reset, and enable signals</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runClockResetEnableChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check VHDL file extension</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runFileExtensionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check generics</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runGenericChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check naming conventions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNameConventionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check package file names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runPackageNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check signal and port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runPortSignalNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check entity and architecture</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runSplitEntityArchitectureChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check module/entity names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runSubsystemNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check top-level subsystem/port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runToplevelNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check delay balancing setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runBalanceDelaysChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for global reset setting for Xilinx and Altera devices</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runGlobalResetChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check inline configurations setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runInlineConfigurationsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for model parameters suited for the HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runModelParamsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for visualization settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runVisualizationChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check blocks with nonzero ulp error</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runNFPULPErrorChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check initial conditions of enabled and triggered subsystems</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runEnTrigInitConChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for invalid top level subsystem</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelAdvisor.runInvalidDUTChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runBlockSupportChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for MATLAB Function block settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runMLFcnBlkChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for obsolete Unit Delay Enabled/Resettable blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runObsoleteDelaysChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for infinite and continuous sample time sources</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSampleTimeChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for unsupported storage class for signal objects</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSignalObjectStorageClassChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for Stateflow chart settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runStateflowChartSettingsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runDisabledLibLinks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runDisabledLibLinks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runReplaceZOHDelayByRTB</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runReplaceZOHDelayByRTB</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runUnconnectedLinesPorts</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runUnconnectedLinesPorts</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runUnresolvedLibLinks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runUnresolvedLibLinks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check architecture name</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runArchitectureNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check clock settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runClockChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check clock, reset, and enable signals</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runClockResetEnableChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check VHDL file extension</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runFileExtensionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check generics</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runGenericChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check naming conventions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNameConventionChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check package file names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runPackageNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check signal and port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runPortSignalNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check entity and architecture</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSplitEntityArchitectureChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check module/entity names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runSubsystemNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check top-level subsystem/port names</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runToplevelNameChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check delay balancing setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runBalanceDelaysChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for global reset setting for Xilinx and Altera devices</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runGlobalResetChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check inline configurations setting</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runInlineConfigurationsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for model parameters suited for the HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runModelParamsChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for visualization settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runVisualizationChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>*FIXME* borrowed_runCharacterEncoding</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.borrowed_runCharacterEncoding</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check blocks with nonzero ulp error</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runNFPULPErrorChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check initial conditions of enabled and triggered subsystems</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runEnTrigInitConChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for invalid top level subsystem</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.ModelChecker.runInvalidDUTChecks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Runtime diagnostics for S-functions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DiagnosticSFcn</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check if Read/Write diagnostics are enabled for Data Store blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DiagnosticDataStoreBlk</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check Data Store Memory blocks for multitasking, strong typing, and shadowing issues</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.DataStoreMemoryBlkIssue</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check that the model is saved in SLX format</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.UseSLXFile</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for foreign characters</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.characterEncoding</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check Model History properties</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.SLXModelProperties</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify masked blocks that specify tabs in mask dialog using MaskTabNames parameter</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckAndUpdateOldMaskTabnames</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check conversion input parameters</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.InputParameters</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model configurations</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.ModelConfigurations</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check subsystem interface</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemInterface</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check subsystem content</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemContent</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Complete conversion</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.ModelReferenceAdvisor.CompleteConversion</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify variant blocks using variant objects with empty conditions</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.emptyVariantObject</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify Model Info blocks that can interact with external source control tools</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ModelInfoKeywordSubstitution</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model and local libraries for SB2SL blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.simulink.SB2SL.Check</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify similar library clones and replace them with links to library blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.CloneDetection.IdentifyStructLibraryClones</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify similar graphical clones and replace them with links to library blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.CloneDetection.IdentifyStructGraphicalClones</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify system constants for use in variant transformation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.IdentifyVariantConstant</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify blocks that qualify for variant transformation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.IdentifyVariantCandidate</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Convert blocks to variants</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.VariantTransform</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Step1. Select data store blocks you want to eliminate</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.DSMElim</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Lookup Table Transformation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.MdlTransformer.LutXform</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check S-functions in the model</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.SFuncAnalyzer</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Open the Upgrade Advisor</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.UpgradeAdvisor.MAEntryPoint</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Upgrade models in a hierarchy</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.UpgradeAdvisor.UpgradeModelHierarchy</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for block upgrade issues</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.Update</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for case mismatches in references to models and libraries</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CaseSensitiveBlockDiagramNames</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Resave in current version of Simulink</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckSavedInCurrentVersion</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Return all simulation outputs as a single Simulink.SimulationOutput object</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckSingleSimulationOutput</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Create baseline to measure the performance. The baseline contains the time to run the simulation and the simulation results (signals logged). To create a baseline, configure the model to log states in the workspace and save the signals in 'Structure with time' format.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CreateBaseline</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Some diagnostics, such as 'Solver data inconsistency', incur run-time overhead during simulation. To improve simulation speed, disable these diagnostics if they are not necessary.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyExpensiveDiagnostics</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Some optimizations, such as 'Block reduction', may be disabled. To improve simulation speed, enable these optimization settings.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyApplicableOptimizations</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Improperly configured lookup table blocks can affect the simulation speed of a model.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.InefficientLookupTableBlocks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Analyze MATLAB System block for code generation capability.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.DetectIntSysObjBlocks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Avoid using Interpreted MATLAB Function blocks.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.DetectIntMATLABFcnBlocks</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Disabling simulation target settings, such as 'Echo expressions without semicolons', can improve simulation speed.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckSimTargetEchoStatus</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check if model reference rebuild setting is set to the proper value</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefRebuildSetting</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Opened and uncommented Scopes can impact simulation performance. This check identifies Scope block, Floating Scope block, and Scope Viewer. Scope Viewer does not support commenting out.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyScopes</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Identify active instrumentation settings on the model. This setting can cause slow simulations due to range collection.</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.Simulink.PerformanceAdvisor.IdentifyActiveMMO</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for virtual bus across model reference boundaries</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckVirtualBusAcrossModelReference</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for parameter initialization and tuning issues</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.ParameterTuning</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check structure parameter usage with bus signals</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.MismatchedBusParams</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check for large number of function arguments from virtual bus across model reference boundary</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>mathworks.design.CheckVirtualBusAcrossModelReferenceArgs</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set Target Device and Synthesis Tool for HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetDevice</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set target reference design options</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetReferenceDesign</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set target interface for HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetInterface</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Set target interface for HDL code generation</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.SetTargetInterfaceAndMode</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for algebraic loops</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckAlgebraicLoop</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for unsupported blocks</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckBlockCompatibility</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model for global sample time settings</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckSampleTime</td></tr>
<tr><td height="20"></td></tr>
<tr><td><b>Title</b></td><td>&#160;&#160;</td><td>Check model compatibility with FPGA-in-the-Loop</td></tr><tr><td><b>TitleID</b></td><td>&#160;&#160;</td><td>com.mathworks.HDL.CheckFIL</td></tr>
<tr><td height="20"></td></tr>