Commit bd0eb2c4 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

COM: audio_first_sin modified

parent 728570b0
--> ml_audio_pkg
audio_first/ml_audio --> ml_audio
-- ------------------------------------------------------------- -- -------------------------------------------------------------
-- --
-- File Name: hdl_prj/hdlsrc/audio_first/ml_audio.vhd -- File Name: hdl_prj/hdlsrc/audio_first_sin/ml_audio.vhd
-- Created: 2021-03-31 11:14:10 -- Created: 2021-04-14 10:22:39
-- --
-- Generated by MATLAB 9.9 and HDL Coder 3.17 -- Generated by MATLAB 9.9 and HDL Coder 3.17
-- --
...@@ -30,14 +30,13 @@ ...@@ -30,14 +30,13 @@
-- ------------------------------------------------------------- -- -------------------------------------------------------------
-- --
-- Module: ml_audio -- Module: ml_audio
-- Source Path: audio_first/ml_audio -- Source Path: audio_first_sin/ml_audio
-- Hierarchy Level: 0 -- Hierarchy Level: 0
-- --
-- ------------------------------------------------------------- -- -------------------------------------------------------------
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
USE work.ml_audio_pkg.ALL;
ENTITY ml_audio IS ENTITY ml_audio IS
PORT( clk : IN std_logic; PORT( clk : IN std_logic;
...@@ -53,23 +52,62 @@ END ml_audio; ...@@ -53,23 +52,62 @@ END ml_audio;
ARCHITECTURE rtl OF ml_audio IS ARCHITECTURE rtl OF ml_audio IS
-- Component Declarations
COMPONENT Sine_HDL_Optimized
PORT( u : IN std_logic_vector(15 DOWNTO 0); -- ufix16_En16
x : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Sine_HDL_Optimized
USE ENTITY work.Sine_HDL_Optimized(rtl);
-- Signals -- Signals
SIGNAL enb : std_logic; SIGNAL enb : std_logic;
SIGNAL audio_i_signed : signed(15 DOWNTO 0); -- sfix16_En15 SIGNAL audio_i_signed : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL switches_i_unsigned : unsigned(9 DOWNTO 0); -- ufix10_En10 SIGNAL switches_i_unsigned : unsigned(9 DOWNTO 0); -- ufix10_En10
SIGNAL Product_cast : signed(10 DOWNTO 0); -- sfix11_En10 SIGNAL Data_Type_Conversion_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL Product_mul_temp : signed(26 DOWNTO 0); -- sfix27_En25 SIGNAL Delay2_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL Product_cast_1 : signed(25 DOWNTO 0); -- sfix26_En25 SIGNAL Sum_out1 : unsigned(15 DOWNTO 0); -- ufix16_En16
SIGNAL Product_out1 : signed(15 DOWNTO 0); -- sfix16_En15 SIGNAL Delay_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay1_reg : vector_of_signed16(0 TO 19); -- sfix16 [20] SIGNAL Gain_cast : signed(31 DOWNTO 0); -- sfix32_En30
SIGNAL Delay1_out1 : signed(15 DOWNTO 0); -- sfix16_En15 SIGNAL Gain_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Sine : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Sine_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL Gain1_cast : signed(31 DOWNTO 0); -- sfix32_En29
SIGNAL Gain1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Sum1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay3_out1 : signed(15 DOWNTO 0); -- sfix16_En15
BEGIN BEGIN
u_Sine_HDL_Optimized : Sine_HDL_Optimized
PORT MAP( u => std_logic_vector(Delay2_out1), -- ufix16_En16
x => Sine -- sfix16_En14
);
audio_i_signed <= signed(audio_i); audio_i_signed <= signed(audio_i);
enb <= clk_enable; enb <= clk_enable;
switches_i_unsigned <= unsigned(switches_i);
Data_Type_Conversion_out1 <= switches_i_unsigned & '0' & '0' & '0' & '0' & '0' & '0';
Sum_out1 <= Data_Type_Conversion_out1 + Delay2_out1;
Delay2_process : PROCESS (clk, rst_n)
BEGIN
IF rst_n = '0' THEN
Delay2_out1 <= to_unsigned(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay2_out1 <= Sum_out1;
END IF;
END IF;
END PROCESS Delay2_process;
Delay_process : PROCESS (clk, rst_n) Delay_process : PROCESS (clk, rst_n)
BEGIN BEGIN
IF rst_n = '0' THEN IF rst_n = '0' THEN
...@@ -82,28 +120,29 @@ BEGIN ...@@ -82,28 +120,29 @@ BEGIN
END PROCESS Delay_process; END PROCESS Delay_process;
switches_i_unsigned <= unsigned(switches_i); Gain_cast <= resize(Delay_out1 & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 32);
Gain_out1 <= Gain_cast(30 DOWNTO 15);
Sine_signed <= signed(Sine);
Gain1_cast <= resize(Sine_signed & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0', 32);
Gain1_out1 <= Gain1_cast(29 DOWNTO 14);
Product_cast <= signed(resize(switches_i_unsigned, 11)); Sum1_out1 <= Gain_out1 + Gain1_out1;
Product_mul_temp <= Delay_out1 * Product_cast;
Product_cast_1 <= Product_mul_temp(25 DOWNTO 0);
Product_out1 <= Product_cast_1(25 DOWNTO 10);
Delay1_process : PROCESS (clk, rst_n) Delay3_process : PROCESS (clk, rst_n)
BEGIN BEGIN
IF rst_n = '0' THEN IF rst_n = '0' THEN
Delay1_reg <= (OTHERS => to_signed(16#0000#, 16)); Delay3_out1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN IF enb = '1' THEN
Delay1_reg(0) <= Product_out1; Delay3_out1 <= Sum1_out1;
Delay1_reg(1 TO 19) <= Delay1_reg(0 TO 18);
END IF; END IF;
END IF; END IF;
END PROCESS Delay1_process; END PROCESS Delay3_process;
Delay1_out1 <= Delay1_reg(19);
audio_o <= std_logic_vector(Delay1_out1); audio_o <= std_logic_vector(Delay3_out1);
ce_out <= clk_enable; ce_out <= clk_enable;
......
vlib work vlib work
vcom ml_audio_pkg.vhd vcom ml_audio_pkg.vhd
vcom Sine_HDL_Optimized.vhd
vcom ml_audio.vhd vcom ml_audio.vhd
--> ml_audio_pkg
audio_first_sin/ml_audio/Sine HDL Optimized --> Sine_HDL_Optimized
audio_first_sin/ml_audio --> ml_audio
-- ------------------------------------------------------------- -- -------------------------------------------------------------
-- --
-- File Name: hdl_prj/hdlsrc/audio_first/ml_audio_pkg.vhd -- File Name: hdl_prj/hdlsrc/audio_first_sin/ml_audio_pkg.vhd
-- Created: 2021-03-31 11:14:10 -- Created: 2021-04-14 10:22:39
-- --
-- Generated by MATLAB 9.9 and HDL Coder 3.17 -- Generated by MATLAB 9.9 and HDL Coder 3.17
-- --
...@@ -14,5 +14,6 @@ USE IEEE.numeric_std.ALL; ...@@ -14,5 +14,6 @@ USE IEEE.numeric_std.ALL;
PACKAGE ml_audio_pkg IS PACKAGE ml_audio_pkg IS
TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0); TYPE vector_of_signed16 IS ARRAY (NATURAL RANGE <>) OF signed(15 DOWNTO 0);
TYPE vector_of_unsigned18 IS ARRAY (NATURAL RANGE <>) OF unsigned(17 DOWNTO 0);
END ml_audio_pkg; END ml_audio_pkg;
<!DOCTYPE HTML> <!DOCTYPE HTML>
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<head> <head>
<title>HDL Check Report for 'audio_first/ml_audio'</title> <title>HDL Check Report for 'audio_first_sin/ml_audio'</title>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8"> <meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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...@@ -46,9 +46,9 @@ ...@@ -46,9 +46,9 @@
<div class="container_192"> <div class="container_192">
<div class="grid_192"> <div class="grid_192">
<div class="page_container"><div class="content_frame"> <div class="page_container"><div class="content_frame">
<h1>HDL Code Generation Check Report for 'audio_first/ml_audio' <h1>HDL Code Generation Check Report for 'audio_first_sin/ml_audio'
<a href="matlab:open_system('audio_first/ml_audio');">open model 'audio_first/ml_audio'</a><BR> <a href="matlab:open_system('audio_first_sin/ml_audio');">open model 'audio_first_sin/ml_audio'</a><BR>
Generated on 2021-03-31 11:14:12</h1> Generated on 2021-04-14 10:22:40</h1>
<H2>No messages, warnings, or errors were found.</H2><BR> <H2>No messages, warnings, or errors were found.</H2><BR>
<BR><BR> </div></div></div></div> <BR><BR> </div></div></div></div>
<div class="grid_192"> <div class="grid_192">
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