Commit c2d2b9c7 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

lab#9 lfsr_fibonacci created

parent 779acb4f
-------------------------------------------------------------------------------
-- Module : lfsr_fibonacci
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY lfsr_fibonacci IS
PORT (
clk_i : IN std_ulogic;
rst_ni : IN std_ulogic;
en_pi : IN std_ulogic;
lfsr_o : OUT std_ulogic_vector(3 DOWNTO 0);
noise_o : OUT std_ulogic;
eoc_po : OUT std_ulogic
);
END lfsr_fibonacci;
ARCHITECTURE rtl OF lfsr_fibonacci IS
SIGNAL q : std_ulogic_vector(3 DOWNTO 0);
SIGNAL d : std_ulogic_vector(3 DOWNTO 0);
SIGNAL count_next_state : unsigned(3 DOWNTO 0);
SIGNAL count_current_state : unsigned(3 DOWNTO 0);
BEGIN
-- counter for eoc_po
count_next_state <= count_current_state + 1;
count_current_state <= "0000" WHEN rst_ni = '0' ELSE
count_next_state WHEN rising_edge(clk_i) AND (en_pi = '1');
eoc_po <= '1' WHEN count_current_state = to_unsigned(15, count_current_state'length) ELSE '0';
-- next state logic
d(0) <= q(1);
d(1) <= q(2);
d(2) <= q(3);
d(3) <= q(1) XOR q(0);
-- current state
q <= "0001" WHEN rst_ni = '0' ELSE
d WHEN rising_edge(clk_i);
-- noise output
noise_o <= q(0);
-- parrallel output
lfsr_o <= q;
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
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