Commit dc567026 authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

COM: Matlab code to vhdl

parent 3c03c86f
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/audio_first/ml_audio.vhd
-- Created: 2021-03-24 12:46:50
--
-- Generated by MATLAB 9.9 and HDL Coder 3.17
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 2.08333e-05
-- Target subsystem base rate: 2.08333e-05
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 2.08333e-05
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- audio_o ce_out 2.08333e-05
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: ml_audio
-- Source Path: audio_first/ml_audio
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY ml_audio IS
PORT( clk : IN std_logic;
rst_n : IN std_logic;
clk_enable : IN std_logic;
switches_i : IN std_logic_vector(9 DOWNTO 0); -- ufix10_En10
audio_i : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En15
ce_out : OUT std_logic;
audio_o : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En15
);
END ml_audio;
ARCHITECTURE rtl OF ml_audio IS
-- Signals
SIGNAL enb : std_logic;
SIGNAL audio_i_signed : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL switches_i_unsigned : unsigned(9 DOWNTO 0); -- ufix10_En10
SIGNAL Product_cast : signed(10 DOWNTO 0); -- sfix11_En10
SIGNAL Product_mul_temp : signed(26 DOWNTO 0); -- sfix27_En25
SIGNAL Product_cast_1 : signed(25 DOWNTO 0); -- sfix26_En25
SIGNAL Product_out1 : signed(15 DOWNTO 0); -- sfix16_En15
SIGNAL Delay1_out1 : signed(15 DOWNTO 0); -- sfix16_En15
BEGIN
audio_i_signed <= signed(audio_i);
enb <= clk_enable;
Delay_process : PROCESS (clk, rst_n)
BEGIN
IF rst_n = '0' THEN
Delay_out1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay_out1 <= audio_i_signed;
END IF;
END IF;
END PROCESS Delay_process;
switches_i_unsigned <= unsigned(switches_i);
Product_cast <= signed(resize(switches_i_unsigned, 11));
Product_mul_temp <= Delay_out1 * Product_cast;
Product_cast_1 <= Product_mul_temp(25 DOWNTO 0);
Product_out1 <= Product_cast_1(25 DOWNTO 10);
Delay1_process : PROCESS (clk, rst_n)
BEGIN
IF rst_n = '0' THEN
Delay1_out1 <= to_signed(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Delay1_out1 <= Product_out1;
END IF;
END IF;
END PROCESS Delay1_process;
audio_o <= std_logic_vector(Delay1_out1);
ce_out <= clk_enable;
END rtl;
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<h1>HDL Code Generation Check Report for 'audio_first/ml_audio'
<a href="matlab:open_system('audio_first/ml_audio');">open model 'audio_first/ml_audio'</a><BR>
Generated on 2021-03-24 12:46:51</h1>
<H2>No messages, warnings, or errors were found.</H2><BR>
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Simulink Coder project marker file. Please don't change it.
slprjVersion: 10.2_082
\ No newline at end of file
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