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Oran Garrity
vlsilab21_garrity_mikschl
Commits
f28188e0
Commit
f28188e0
authored
Apr 15, 2021
by
Manuel Mikschl
Browse files
lab#6: calculator extending part 2 (testing)
parent
00520ad2
Changes
4
Hide whitespace changes
Inline
Side-by-side
matlab/audio/audio_first_sin.slx.autosave
deleted
100644 → 0
View file @
00520ad2
File deleted
pnr/de1_calculator/de1_calculator_pins.tcl
View file @
f28188e0
...
...
@@ -20,6 +20,7 @@ set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR
[
6
]
set_location_assignment PIN_U18 -to LEDR
[
7
]
set_location_assignment PIN_R18 -to LEDR
[
8
]
set_location_assignment PIN_R17 -to LEDR
[
9
]
set_location_assignment PIN_J2 -to HEX0
[
0
]
set_location_assignment PIN_J1 -to HEX0
[
1
]
set_location_assignment PIN_H2 -to HEX0
[
2
]
...
...
src/#twosc2sm_rtl.vhd#
0 → 100644
View file @
f28188e0
-------------------------------------------------------------------------------
-- Module : twosc2sm
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Revisions : see end of file
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY twosc2sm IS
PORT (value_sc_i : IN std_ulogic_vector(3 DOWNTO 0);
value_sm_o : OUT std_ulogic_vector(3 DOWNTO 0);
sign_o : OUT std_ulogic;
overflow_o : OUT std_ulogic
);
END twosc2sm;
ARCHITECTURE rtl OF twosc2sm IS
SIGNAL value_3bit : unsigned(2 DOWNTO 0);
SIGNAL value_4bit : unsigned(3 DOWNTO 0);
BEGIN
sign_output : sign_o <= value_sc_i(3);
value_3bit_signal : value_3bit <= unsigned(value_sc_i(2 DOWNTO 0));
value_4bit_signal : value_4bit <= resize(value_3bit, value_sm_o'length);
value_sm_output: value_sm_o <= std_ulogic_vector(value_4bit);
overflow_output : overflow_o <= '1' WHE
END rtl;
-------------------------------------------------------------------------------
-- Revisions:
-- ----------
-- $Id:$
-------------------------------------------------------------------------------
src/de1_calculator_structure.vhd
View file @
f28188e0
...
...
@@ -15,7 +15,7 @@ USE IEEE.numeric_std.ALL;
ENTITY
de1_calculator
IS
PORT
(
SW
:
IN
std_ulogic_vector
(
7
DOWNTO
0
);
-- Toggle Switch[7:0]
LEDR
:
OUT
std_ulogic_vector
(
8
DOWNTO
0
);
-- LED Red[
7
:0]
LEDR
:
OUT
std_ulogic_vector
(
9
DOWNTO
0
);
-- LED Red[
9
:0]
HEX0
:
OUT
std_ulogic_vector
(
6
DOWNTO
0
)
-- Seven Segment Digit 0
);
END
de1_calculator
;
...
...
@@ -39,6 +39,10 @@ ARCHITECTURE structure OF de1_calculator IS
SIGNAL
b
:
signed
(
3
DOWNTO
0
);
SIGNAL
sum
:
signed
(
3
DOWNTO
0
);
SIGNAL
sum_sm
:
std_ulogic_vector
(
3
DOWNTO
0
);
SIGNAL
locala
:
signed
(
4
DOWNTO
0
);
SIGNAL
localb
:
signed
(
4
DOWNTO
0
);
SIGNAL
localsum
:
signed
(
4
DOWNTO
0
);
SIGNAL
overflow
:
std_ulogic
;
BEGIN
...
...
@@ -46,6 +50,16 @@ BEGIN
a
<=
signed
(
SW
(
3
DOWNTO
0
));
b
<=
signed
(
SW
(
7
DOWNTO
4
));
-- resize a and b to 5 Bit length
locala
<=
resize
(
a
,
5
);
localb
<=
resize
(
b
,
5
);
-- add the 5 bit values
localsum
<=
locala
+
localb
;
-- check if overflow
overflow
<=
'1'
WHEN
localsum
(
3
)
/=
localsum
(
4
)
ELSE
'0'
;
-- add the operands
sum
<=
resize
(
a
,
sum
'length
)
+
resize
(
b
,
sum
'length
);
...
...
@@ -54,6 +68,7 @@ BEGIN
-- LEDR(3) <= '0';
LEDR
(
7
DOWNTO
4
)
<=
SW
(
7
DOWNTO
4
);
-- LEDR(7) <= '0';
LEDR
(
9
)
<=
overflow
;
-- convert 2'sc to sign-magnitude
signmag_sum
:
twosc2sm
...
...
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