Commit fc212f2b authored by Manuel Mikschl's avatar Manuel Mikschl
Browse files

Lab#10 tone in game

parent 1b231174
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_R22 -to KEY[0]
set_location_assignment PIN_R21 -to KEY[1]
set_location_assignment PIN_U22 -to LEDG[0]
set_location_assignment PIN_U21 -to LEDG[1]
set_location_assignment PIN_A3 -to I2C_SCLK
set_location_assignment PIN_B3 -to I2C_SDAT
set_location_assignment PIN_A6 -to AUD_ADCLRCK
set_location_assignment PIN_B6 -to AUD_ADCDAT
set_location_assignment PIN_A5 -to AUD_DACLRCK
set_location_assignment PIN_B5 -to AUD_DACDAT
set_location_assignment PIN_B4 -to AUD_XCK
set_location_assignment PIN_A4 -to AUD_BCLK
# ----------------------------------------------------------------------------
......@@ -19,5 +19,15 @@ set_location_assignment PIN_B6 -to AUD_ADCDAT
set_location_assignment PIN_A5 -to AUD_DACLRCK
set_location_assignment PIN_B5 -to AUD_DACDAT
set_location_assignment PIN_B4 -to AUD_XCK
set_location_assignment PIN_A4 -to AUD_BCLK
set_location_assignment PIN_A4 -to AUD_BCLK
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_M1 -to SW[8]
set_location_assignment PIN_L2 -to SW[9]
# ----------------------------------------------------------------------------
......@@ -10,7 +10,7 @@ entity de1_play is
KEY : in std_ulogic_vector(1 downto 0);
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_logic;
SW_i : in std_ulogic_vector(9 downto 0);
SW : in std_ulogic_vector(9 downto 0);
AUD_ADCLRCK : out std_ulogic;
AUD_ADCDAT : in std_ulogic;
AUD_DACLRCK : out std_ulogic;
......@@ -150,7 +150,7 @@ begin
dv_i => adc_valid,
audio_i => adc_data,
audio_o => audio_o,
switches_i => SW_i);
switches_i => SW);
-- select if tone is activated or not
dac_data <= audio_o WHEN tone_o = '1' ELSE "0000000000000000";
......
......@@ -14,6 +14,7 @@ component de1_play is
KEY : in std_ulogic_vector(1 downto 0); -- key(1..0)
I2C_SCLK : out std_ulogic;
I2C_SDAT : inout std_logic;
SW : in std_ulogic_vector(9 downto 0);
AUD_ADCLRCK : out std_ulogic;
AUD_ADCDAT : in std_ulogic;
AUD_DACLRCK : out std_ulogic;
......@@ -28,6 +29,7 @@ end component;
-- definition of a clock period
constant period : time := 10 ns;
constant onesec : time := 20 ns;
-- switch for clock generator
signal clken_p : boolean := true;
......@@ -45,6 +47,8 @@ end component;
signal test_tone : real;
signal test_tone_quantized : signed(15 downto 0);
signal bit_count : integer range 0 to 31;
signal switches : std_ulogic_vector(9 downto 0);
begin
......@@ -94,6 +98,7 @@ begin
KEY(0) => rst_ni,
KEY(1) => key,
I2C_SCLK => i2c_clk,
SW => switches,
I2C_SDAT => i2c_dat,
AUD_ADCLRCK => aud_adclrck,
AUD_ADCDAT => aud_adcdat,
......
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