Commit ffba466e authored by Johann Faerber's avatar Johann Faerber
Browse files

lab exercices #1 .. #6 from year ss2020

parent fb6fd85c
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#############################################################################
# Parser keywords
#############################################################################
# Polarity
HIGHActiveSuffix=_pi
LOWActiveSuffix=_ni
# Special ports
#resetName=rst_n
#clockName=clk
resetName=rst_ni
clockName=clk_i
#resetName=rst_pi
#clockName=clk_i
#resetName=rst_i
#clockName=clk_i
#clockName=CLOCK_50
#resetName=KEY
#resetName=reset
#clockName=clock
# Default label to print above entity box. Leave empty if no label is desired
default_label=
#############################################################################
# Font settings
#############################################################################
# Label
label.fontFamily=Arial
label.fontSize=10pt
label.fontWeight=normal
# Entity
entity.fontFamily=Arial
entity.fontSize=12pt
entity.fontWeight=bold
#Port
port.fontFamily=Arial
port.fontSize=12pt
port.fontWeight=normal
# Generic signal
genericSignal.fontFamily=Arial
genericSignal.fontSize=10pt
genericSignal.fontWeight=normal
# Vector
vector.fontFamily=Arial
vector.fontSize=10pt
vector.fontWeight=normal
#############################################################################
# Shape settings
#############################################################################
# Margin
vertical_Margin=0.5
horizontal_Margin=0.5
fixed_Width=0
# Label
label.stroke=none
label.strokeWidth=0.00cm
label.strokeColor=#000000
label.fill=none
label.fillColor=#FFFFFF
# Entity
entity.stroke=solid
entity.strokeWidth=0.05cm
entity.strokeColor=#000000
entity.fill=solid
entity.fillColor=#FFFFFF
# Port
port.stroke=none
port.strokeWidth=0.00cm
port.strokeColor=#FFF
port.fill=none
port.fillColor=#FFFFFF
# Connector
connector.stroke=solid
connector.strokeWidth=0.025cm
connector.strokeColor=#000000
connector.fill=solid
connector.fillColor=#FFFFFF
# Generics
generics.stroke=solid
generics.strokeWidth=0.02cm
generics.strokeColor=#BFBFBF
generics.fill=solid
generics.fillColor=#F2F2F2
# Generic signal
genericSignal.stroke=none
genericSignal.strokeWidth=0.00cm
genericSignal.strokeColor=#C2C2C2
genericSignal.fill=none
genericSignal.fillColor=#FFFFFF
#############################################################################
# Doku Wiki markup settings
#############################################################################
DokuWiki.enableExport=0
# If left empty the output files will be placed in the same directory where the executable is located.
# Both absolute and relative path are working
DokuWiki.outputPath=dokuwiki
#############################################################################
# Markdown settings
#############################################################################
Markdown.enableExport=0
# If left empty the output files will be placed in the same directory where the executable is located.
# Both absolute and relative path are working
Markdown.outputPath=markdown
#############################################################################
# LaTeX settings
#############################################################################
LaTeX.enableExport=0
# If left empty the output files will be placed in the same directory where the executable is located.
# Both absolute and relative path are working
LaTeX.outputPath=latex
# VEC can add a 'table' environment to label and place the actual tabular element.
# VEC will use the entity name as caption and label
LaTeX.addTable=1
LaTeX.centering=1
LaTeX.caption=1
LaTeX.label=1
#############################################################################
# Table export settings
#############################################################################
# Set the entity information the table should contain
Table.exportType=1
Table.exportDirection=1
Table.exportPolarity=1
Table.exportDescription=1
Table.exportBlank1=0
Table.exportBlank2=0
# Export generics. Generate a seperate table for generic signals
Table.exportGenerics=1
# Heading formatting
Table.boldHeadings=1
# Column alignments
Table.centeredName=0
Table.centeredType=0
Table.centeredDirection=1
Table.centeredPolarity=1
Table.centeredDescription=0
Table.centeredBlank=0
Table.centeredGenericName=0
Table.centeredGenericType=0
Table.centeredGenericDefaultValue=0
# Column headings
Table.Name_heading=Name
Table.Type_heading=Type
Table.Direction_heading=Direction
Table.Polarity_heading=Polarity
Table.Description_heading=Description
Table.Blank1_heading=Blank1
Table.Blank2_heading=Blank2
Table.GenericName=Name
Table.GenericType=Type
Table.GenericDefaultValue=Default value
# Captions for the port directions
Table.caption_IN=IN
Table.caption_OUT=OUT
Table.caption_INOUT=INOUT
Table.caption_BUFFER=BUFFER
Table.caption_LINKAGE=LINKAGE
# Polarity labels
Table.caption_HIGHactive=HIGH
Table.caption_LOWactive=LOW
# Vector settings
Table.combineNameAndType=0
Table.showArrayLength=1
Table.arrayNotation=1
#############################################################################
# PATH settings
#############################################################################
# Path to LibreOffice executable.
# e.g. for WINDOWS
# C:\Program Files (x86)\LibreOffice 4.0\program\soffice.exe
# e.g. for UNIX platforms
# /usr/bin/soffice
#PATH.soffice=C:\Program Files (x86)\LibreOffice 3.6\program\soffice.exe
PATH.soffice=/usr/bin/soffice
#############################################################################
# FODG Export
#############################################################################
FODG.enableExport=1
# If left empty the output files will be placed in the same directory where the executable is located
#FODG.outputPath=fodg
FODG.outputPath=.
#############################################################################
# PNG Export
#############################################################################
PNG.enableExport=1
# If left empty the output files will be placed in the same directory where the executable is located
#PNG.outputPath=png
PNG.outputPath=.
#############################################################################
# SVG Export
#############################################################################
SVG.enableExport=0
# If left empty the output files will be placed in the same directory where the executable is located
#SVG.outputPath=svg
SVG.outputPath=.
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_R20 -to LEDR
# ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = cnt4up
PROJECT = $(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
# DEMMK
# FAMILY = "MAX II"
# DEVICE = EPM2210F324C3
# PROGFILEEXT = pof
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
#PROGFILEEXT = sof
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
#PROGFILEEXT = sof
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/$(PROJECT)_structure.vhd
include ../makefile
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_R20 -to LEDR
# ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = cntupen
PROJECT = $(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
# DEMMK
# FAMILY = "MAX II"
# DEVICE = EPM2210F324C3
# PROGFILEEXT = pof
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
#PROGFILEEXT = sof
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
#PROGFILEEXT = sof
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/$(PROJECT)_rtl.vhd
include ../makefile
## ----------------------------------------------------------------------------
## Description:
## ------------
## assumes the following design directory structure as prerequisite
##
## DigitaltechnikPraktikum
## |
## +---src
## | and2gate_equation.vhd
## | invgate_equation.vhd
## | mux2to1_structure.vhd
## | or2gate_equation.vhd
## | t_mux2to1.vhd
## | de1_mux2to1_structure.vhd
## |
## +---sim
## | | makefile
## | |
## | \---mux2to1
## | makefile
## | makefile.sources
## |
## +---pnr
## | | makefile
## | |
## | \---de1_mux2to1
## | de1_mux2to1_pins.tcl
## | makefile
## |
## \---scripts
## de1_pin_assignments_minimumio.csv
## de1_pin_assignments_minimumio.tcl
## modelsim.ini
## quartus_project_settings.tcl
## ----------------------------------------------------------------------------
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
# ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = add1
PROJECT = de1_$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
# DEMMK
# FAMILY = "MAX II"
# DEVICE = EPM2210F324C3
# PROGFILEEXT = pof
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
#PROGFILEEXT = sof
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
#PROGFILEEXT = sof
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/$(PROJECT)_structure.vhd
include ../makefile
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_W12 -to SW[4]
set_location_assignment PIN_U12 -to SW[5]
set_location_assignment PIN_U11 -to SW[6]
set_location_assignment PIN_M2 -to SW[7]
set_location_assignment PIN_M1 -to SW[8]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_T18 -to LEDR[4]
set_location_assignment PIN_V19 -to LEDR[5]
set_location_assignment PIN_Y18 -to LEDR[6]
set_location_assignment PIN_U18 -to LEDR[7]
set_location_assignment PIN_R18 -to LEDR[8]
set_location_assignment PIN_U22 -to LEDG[0]
set_location_assignment PIN_U21 -to LEDG[1]
set_location_assignment PIN_V22 -to LEDG[2]
set_location_assignment PIN_V21 -to LEDG[3]
set_location_assignment PIN_W22 -to LEDG[4]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
set_location_assignment PIN_E1 -to HEX1[0]
set_location_assignment PIN_H6 -to HEX1[1]
set_location_assignment PIN_H5 -to HEX1[2]
set_location_assignment PIN_H4 -to HEX1[3]
set_location_assignment PIN_G3 -to HEX1[4]
set_location_assignment PIN_D2 -to HEX1[5]
set_location_assignment PIN_D1 -to HEX1[6]
set_location_assignment PIN_G5 -to HEX2[0]
set_location_assignment PIN_G6 -to HEX2[1]
set_location_assignment PIN_C2 -to HEX2[2]
set_location_assignment PIN_C1 -to HEX2[3]
set_location_assignment PIN_E3 -to HEX2[4]
set_location_assignment PIN_E4 -to HEX2[5]
set_location_assignment PIN_D3 -to HEX2[6]
set_location_assignment PIN_H12 -to GPO_1[0]
set_location_assignment PIN_H13 -to GPO_1[1]
set_location_assignment PIN_L1 -to CLOCK_50
set_location_assignment PIN_H14 -to GPI_1_2
# ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg
## ----------------------------------------------------------------------------
## Description: This makefile allows automating design flow with Quartus,
## it is based on a design directory structure described in
## ../makefile
## ----------------------------------------------------------------------------
###################################################################
# Project Configuration:
#
# - assign variable SIM_PROJECT_NAME with the top level project name
# - add additional VHDL sources to SOURCE_FILES, if necessary
#
# Prerequisite:
# - mandatory design directory structure (see end of file)
# - assumes file name of top level entity de1_$(PROJECT)_structure.vhd
###################################################################
SIM_PROJECT_NAME = add4
PROJECT = de1_$(SIM_PROJECT_NAME)
# Prototype Board FPGA family and device settings
# DE1
FAMILY = "Cyclone II"
DEVICE = EP2C20F484C7
PROGFILEEXT = sof
# DEMMK
# FAMILY = "MAX II"
# DEVICE = EPM2210F324C3
# PROGFILEEXT = pof
# DE2
#FAMILY = "Cyclone II"
#DEVICE = EP2C35F484C7
#PROGFILEEXT = sof
# DE0
#FAMILY = "Cyclone IV E"
#DEVICE = EP4CE22F17C6
#PROGFILEEXT = sof
# Here the VHDL files for synthesis are defined.
include ../../sim/$(SIM_PROJECT_NAME)/makefile.sources
# Add the toplevel fpga vhdl file
SOURCE_FILES = $(SYN_SOURCE_FILES) \
../../src/binto7segment_truthtable.vhd \
../../src/$(PROJECT)_structure.vhd
include ../makefile
# assign pin locations to a quartus project
#----------------------------------------------------------------------
# Pin Assignments
set_location_assignment PIN_L22 -to SW[0]
set_location_assignment PIN_L21 -to SW[1]
set_location_assignment PIN_M22 -to SW[2]
set_location_assignment PIN_V12 -to SW[3]
set_location_assignment PIN_R20 -to LEDR[0]
set_location_assignment PIN_R19 -to LEDR[1]
set_location_assignment PIN_U19 -to LEDR[2]
set_location_assignment PIN_Y19 -to LEDR[3]
set_location_assignment PIN_J2 -to HEX0[0]
set_location_assignment PIN_J1 -to HEX0[1]
set_location_assignment PIN_H2 -to HEX0[2]
set_location_assignment PIN_H1 -to HEX0[3]
set_location_assignment PIN_F2 -to HEX0[4]
set_location_assignment PIN_F1 -to HEX0[5]
set_location_assignment PIN_E2 -to HEX0[6]
# ----------------------------------------------------------------------------
## ----------------------------------------------------------------------------
## Script : makefile
## ----------------------------------------------------------------------------
## Author : Johann Faerber, Friedrich Beckmann
## Company : University of Applied Sciences Augsburg