Model Advisor Customization

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Title  Check rapid accelerator signal logging
TitleID  mathworks.design.CheckRapidAcceleratorSignalLogging
Title  Identify Model Variants blocks and convert those to Variant Subsystem blocks containing Model block choices
TitleID  mathworks.design.ConvertMdlrefVarToVSS
Title  Check get_param calls for block CompiledSampleTime
TitleID  mathworks.design.CallsGetParamCompiledSampleTime
Title  Identify unconnected lines, input ports, and output ports
TitleID  mathworks.design.UnconnectedLinesPorts
Title  Check root model Inport block specifications
TitleID  mathworks.design.RootInportSpec
Title  Check diagnostic settings ignored during accelerated model reference simulation
TitleID  mathworks.design.ModelRefSIMConfigCompliance
Title  Check for parameter tunability information ignored for referenced models
TitleID  mathworks.design.ParamTunabilityIgnored
Title  Check for implicit signal resolution
TitleID  mathworks.design.ImplicitSignalResolution
Title  Check for optimal bus virtuality
TitleID  mathworks.design.OptBusVirtuality
Title  Check for calls to slDataTypeAndScale()
TitleID  mathworks.design.CallslDataTypeAndScale
Title  Check for Discrete-Time Integrator blocks with initial condition uncertainty
TitleID  mathworks.design.DiscreteTimeIntegratorInitCondition
Title  Identify disabled library links
TitleID  mathworks.design.DisabledLibLinks
Title  Identify parameterized library links
TitleID  mathworks.design.ParameterizedLibLinks
Title  Identify unresolved library links
TitleID  mathworks.design.UnresolvedLibLinks
Title  Identify configurable subsystem template blocks having the instances in the model for converting to variant subsystem blocks.
TitleID  mathworks.design.CSStoVSSConvert
Title  Check usage of function-call connections
TitleID  mathworks.design.CheckForProperFcnCallUsage
Title  Check and update masked blocks in library to use promoted parameters
TitleID  mathworks.design.CheckAndUpdateOldMaskedBuiltinBlocks
Title  Check and update mask image display commands with unnecessary imread() function calls
TitleID  mathworks.design.CheckMaskDisplayImageFormat
Title  Check and update mask to affirm icon drawing commands dependency on mask workspace
TitleID  mathworks.design.CheckMaskRunInitFlag
Title  
TitleID  com.mathworks.hdlssc.ssccodegenadvisor.workflowObjectCheck
Title  Extract equations
TitleID  com.mathworks.hdlssc.ssccodegenadvisor.getStateSpaceParametersTask
Title  Set Target Frequency
TitleID  com.mathworks.HDL.SetGenericTargetFrequency
Title  Set Target Frequency
TitleID  com.mathworks.HDL.SetTargetFrequency
Title  Check model-level settings for HDL code generation
TitleID  com.mathworks.HDL.CheckGlobalSettings
Title  Set basic options for RTL code generation
TitleID  com.mathworks.HDL.SetBasicOptions
Title  Set report options
TitleID  com.mathworks.HDL.SetReportOptions
Title  Set advanced options
TitleID  com.mathworks.HDL.SetAdvancedOptions
Title  Set Optimization Options
TitleID  com.mathworks.HDL.SetOptimizationOptions
Title  Set testbench options
TitleID  com.mathworks.HDL.SetTBOptions
Title  Verify generated RTL code with a HDL Cosimulation testbench
TitleID  com.mathworks.HDL.VerifyCosim
Title  Create synthesis tool project
TitleID  com.mathworks.HDL.CreateProject
Title  Run logic synthesis for specified FPGA device
TitleID  com.mathworks.HDL.RunLogicSynthesis
Title  Run mapping for specified FPGA device
TitleID  com.mathworks.HDL.RunMapping
Title  Run place and route for specified FPGA device
TitleID  com.mathworks.HDL.RunPandR
Title  Run logic synthesis for specified FPGA device
TitleID  com.mathworks.HDL.RunVivadoSynthesis
Title  Run place and route for specified FPGA device
TitleID  com.mathworks.HDL.RunImplementation
Title  Annotate synthesis result back to the Simulink model
TitleID  com.mathworks.HDL.AnnotateModel
Title  Generate programming file for specified FPGA device
TitleID  com.mathworks.HDL.GenerateBitstream
Title  Program target FPGA device
TitleID  com.mathworks.HDL.ProgramDevice
Title  Generate Simulink Real-Time interface
TitleID  com.mathworks.HDL.GeneratexPCInterface
Title  Set FPGA-in-the-Loop Options
TitleID  com.mathworks.HDL.FILOption
Title  Generate FPGA programming file and FPGA-in-the-Loop testbench model
TitleID  com.mathworks.HDL.RunFIL
Title  Generate FPGA programming file for USRP(R) board. The FPGA project is generated first. Then syntax checking is performed on the HDL code. If no error was found in FPGA project generation and syntax checking, FPGA programming file generation process will start in an external command-line window.
TitleID  com.mathworks.HDL.RunUSRP
Title  Create project for embedded system tool
TitleID  com.mathworks.HDL.EmbeddedProject
Title  Generate a software interface for the IP core
TitleID  com.mathworks.HDL.EmbeddedModelGen
Title  Generate a software interface model with IP core driver blocks.
TitleID  com.mathworks.HDL.EmbeddedCustomModelGen
Title  Synthesis and generate bitstream for embedded system on FPGA
TitleID  com.mathworks.HDL.EmbeddedSystemBuild
Title  Program target FPGA device
TitleID  com.mathworks.HDL.EmbeddedDownload
Title  Check for unsupported blocks
TitleID  com.mathworks.HDL.ModelAdvisor.runBlockSupportChecks
Title  Check for MATLAB Function block settings
TitleID  com.mathworks.HDL.ModelAdvisor.runMLFcnBlkChecks
Title  Check for obsolete Unit Delay Enabled/Resettable blocks
TitleID  com.mathworks.HDL.ModelAdvisor.runObsoleteDelaysChecks
Title  Check for infinite and continuous sample time sources
TitleID  com.mathworks.HDL.ModelAdvisor.runSampleTimeChecks
Title  Check for unsupported storage class for signal objects
TitleID  com.mathworks.HDL.ModelAdvisor.runSignalObjectStorageClassChecks
Title  Check for Stateflow chart settings
TitleID  com.mathworks.HDL.ModelAdvisor.runStateflowChartSettingsChecks
Title  Check architecture name
TitleID  com.mathworks.HDL.ModelAdvisor.runArchitectureNameChecks
Title  Check clock settings
TitleID  com.mathworks.HDL.ModelAdvisor.runClockChecks
Title  Check clock, reset, and enable signals
TitleID  com.mathworks.HDL.ModelAdvisor.runClockResetEnableChecks
Title  Check VHDL file extension
TitleID  com.mathworks.HDL.ModelAdvisor.runFileExtensionChecks
Title  Check generics
TitleID  com.mathworks.HDL.ModelAdvisor.runGenericChecks
Title  Check naming conventions
TitleID  com.mathworks.HDL.ModelAdvisor.runNameConventionChecks
Title  Check package file names
TitleID  com.mathworks.HDL.ModelAdvisor.runPackageNameChecks
Title  Check signal and port names
TitleID  com.mathworks.HDL.ModelAdvisor.runPortSignalNameChecks
Title  Check entity and architecture
TitleID  com.mathworks.HDL.ModelAdvisor.runSplitEntityArchitectureChecks
Title  Check module/entity names
TitleID  com.mathworks.HDL.ModelAdvisor.runSubsystemNameChecks
Title  Check top-level subsystem/port names
TitleID  com.mathworks.HDL.ModelAdvisor.runToplevelNameChecks
Title  Check delay balancing setting
TitleID  com.mathworks.HDL.ModelAdvisor.runBalanceDelaysChecks
Title  Check for global reset setting for Xilinx and Altera devices
TitleID  com.mathworks.HDL.ModelAdvisor.runGlobalResetChecks
Title  Check inline configurations setting
TitleID  com.mathworks.HDL.ModelAdvisor.runInlineConfigurationsChecks
Title  Check for model parameters suited for the HDL code generation
TitleID  com.mathworks.HDL.ModelAdvisor.runModelParamsChecks
Title  Check for visualization settings
TitleID  com.mathworks.HDL.ModelAdvisor.runVisualizationChecks
Title  Check blocks with nonzero ulp error
TitleID  com.mathworks.HDL.ModelAdvisor.runNFPULPErrorChecks
Title  Check initial conditions of enabled and triggered subsystems
TitleID  com.mathworks.HDL.ModelAdvisor.runEnTrigInitConChecks
Title  Check for invalid top level subsystem
TitleID  com.mathworks.HDL.ModelAdvisor.runInvalidDUTChecks
Title  Check for unsupported blocks
TitleID  com.mathworks.HDL.ModelChecker.runBlockSupportChecks
Title  Check for MATLAB Function block settings
TitleID  com.mathworks.HDL.ModelChecker.runMLFcnBlkChecks
Title  Check for obsolete Unit Delay Enabled/Resettable blocks
TitleID  com.mathworks.HDL.ModelChecker.runObsoleteDelaysChecks
Title  Check for infinite and continuous sample time sources
TitleID  com.mathworks.HDL.ModelChecker.runSampleTimeChecks
Title  Check for unsupported storage class for signal objects
TitleID  com.mathworks.HDL.ModelChecker.runSignalObjectStorageClassChecks
Title  Check for Stateflow chart settings
TitleID  com.mathworks.HDL.ModelChecker.runStateflowChartSettingsChecks
Title  *FIXME* borrowed_runDisabledLibLinks
TitleID  com.mathworks.HDL.ModelChecker.borrowed_runDisabledLibLinks
Title  *FIXME* borrowed_runReplaceZOHDelayByRTB
TitleID  com.mathworks.HDL.ModelChecker.borrowed_runReplaceZOHDelayByRTB
Title  *FIXME* borrowed_runUnconnectedLinesPorts
TitleID  com.mathworks.HDL.ModelChecker.borrowed_runUnconnectedLinesPorts
Title  *FIXME* borrowed_runUnresolvedLibLinks
TitleID  com.mathworks.HDL.ModelChecker.borrowed_runUnresolvedLibLinks
Title  Check architecture name
TitleID  com.mathworks.HDL.ModelChecker.runArchitectureNameChecks
Title  Check clock settings
TitleID  com.mathworks.HDL.ModelChecker.runClockChecks
Title  Check clock, reset, and enable signals
TitleID  com.mathworks.HDL.ModelChecker.runClockResetEnableChecks
Title  Check VHDL file extension
TitleID  com.mathworks.HDL.ModelChecker.runFileExtensionChecks
Title  Check generics
TitleID  com.mathworks.HDL.ModelChecker.runGenericChecks
Title  Check naming conventions
TitleID  com.mathworks.HDL.ModelChecker.runNameConventionChecks
Title  Check package file names
TitleID  com.mathworks.HDL.ModelChecker.runPackageNameChecks
Title  Check signal and port names
TitleID  com.mathworks.HDL.ModelChecker.runPortSignalNameChecks
Title  Check entity and architecture
TitleID  com.mathworks.HDL.ModelChecker.runSplitEntityArchitectureChecks
Title  Check module/entity names
TitleID  com.mathworks.HDL.ModelChecker.runSubsystemNameChecks
Title  Check top-level subsystem/port names
TitleID  com.mathworks.HDL.ModelChecker.runToplevelNameChecks
Title  Check delay balancing setting
TitleID  com.mathworks.HDL.ModelChecker.runBalanceDelaysChecks
Title  Check for global reset setting for Xilinx and Altera devices
TitleID  com.mathworks.HDL.ModelChecker.runGlobalResetChecks
Title  Check inline configurations setting
TitleID  com.mathworks.HDL.ModelChecker.runInlineConfigurationsChecks
Title  Check for model parameters suited for the HDL code generation
TitleID  com.mathworks.HDL.ModelChecker.runModelParamsChecks
Title  Check for visualization settings
TitleID  com.mathworks.HDL.ModelChecker.runVisualizationChecks
Title  *FIXME* borrowed_runCharacterEncoding
TitleID  com.mathworks.HDL.ModelChecker.borrowed_runCharacterEncoding
Title  Check blocks with nonzero ulp error
TitleID  com.mathworks.HDL.ModelChecker.runNFPULPErrorChecks
Title  Check initial conditions of enabled and triggered subsystems
TitleID  com.mathworks.HDL.ModelChecker.runEnTrigInitConChecks
Title  Check for invalid top level subsystem
TitleID  com.mathworks.HDL.ModelChecker.runInvalidDUTChecks
Title  Runtime diagnostics for S-functions
TitleID  mathworks.design.DiagnosticSFcn
Title  Check if Read/Write diagnostics are enabled for Data Store blocks
TitleID  mathworks.design.DiagnosticDataStoreBlk
Title  Check Data Store Memory blocks for multitasking, strong typing, and shadowing issues
TitleID  mathworks.design.DataStoreMemoryBlkIssue
Title  Check that the model is saved in SLX format
TitleID  mathworks.design.UseSLXFile
Title  Check model for foreign characters
TitleID  mathworks.design.characterEncoding
Title  Check Model History properties
TitleID  mathworks.design.SLXModelProperties
Title  Identify masked blocks that specify tabs in mask dialog using MaskTabNames parameter
TitleID  mathworks.design.CheckAndUpdateOldMaskTabnames
Title  Check conversion input parameters
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.InputParameters
Title  Check model configurations
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.ModelConfigurations
Title  Check subsystem interface
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemInterface
Title  Check subsystem content
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.SubsystemContent
Title  Complete conversion
TitleID  com.mathworks.Simulink.ModelReferenceAdvisor.CompleteConversion
Title  Identify variant blocks using variant objects with empty conditions
TitleID  mathworks.design.emptyVariantObject
Title  Identify Model Info blocks that can interact with external source control tools
TitleID  mathworks.design.ModelInfoKeywordSubstitution
Title  Check model and local libraries for SB2SL blocks
TitleID  mathworks.simulink.SB2SL.Check
Title  Identify similar library clones and replace them with links to library blocks
TitleID  com.mathworks.Simulink.CloneDetection.IdentifyStructLibraryClones
Title  Identify similar graphical clones and replace them with links to library blocks
TitleID  com.mathworks.Simulink.CloneDetection.IdentifyStructGraphicalClones
Title  Identify system constants for use in variant transformation
TitleID  com.mathworks.Simulink.MdlTransformer.IdentifyVariantConstant
Title  Identify blocks that qualify for variant transformation
TitleID  com.mathworks.Simulink.MdlTransformer.IdentifyVariantCandidate
Title  Convert blocks to variants
TitleID  com.mathworks.Simulink.MdlTransformer.VariantTransform
Title  Step1. Select data store blocks you want to eliminate
TitleID  com.mathworks.Simulink.MdlTransformer.DSMElim
Title  Lookup Table Transformation
TitleID  com.mathworks.Simulink.MdlTransformer.LutXform
Title  Check S-functions in the model
TitleID  mathworks.design.SFuncAnalyzer
Title  Open the Upgrade Advisor
TitleID  com.mathworks.Simulink.UpgradeAdvisor.MAEntryPoint
Title  Upgrade models in a hierarchy
TitleID  com.mathworks.Simulink.UpgradeAdvisor.UpgradeModelHierarchy
Title  Check model for block upgrade issues
TitleID  mathworks.design.Update
Title  Check for case mismatches in references to models and libraries
TitleID  mathworks.design.CaseSensitiveBlockDiagramNames
Title  Resave in current version of Simulink
TitleID  mathworks.design.CheckSavedInCurrentVersion
Title  Return all simulation outputs as a single Simulink.SimulationOutput object
TitleID  mathworks.design.CheckSingleSimulationOutput
Title  Create baseline to measure the performance. The baseline contains the time to run the simulation and the simulation results (signals logged). To create a baseline, configure the model to log states in the workspace and save the signals in 'Structure with time' format.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CreateBaseline
Title  Some diagnostics, such as 'Solver data inconsistency', incur run-time overhead during simulation. To improve simulation speed, disable these diagnostics if they are not necessary.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyExpensiveDiagnostics
Title  Some optimizations, such as 'Block reduction', may be disabled. To improve simulation speed, enable these optimization settings.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyApplicableOptimizations
Title  Improperly configured lookup table blocks can affect the simulation speed of a model.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.InefficientLookupTableBlocks
Title  Analyze MATLAB System block for code generation capability.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.DetectIntSysObjBlocks
Title  Avoid using Interpreted MATLAB Function blocks.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.DetectIntMATLABFcnBlocks
Title  Disabling simulation target settings, such as 'Echo expressions without semicolons', can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimTargetEchoStatus
Title  Check if model reference rebuild setting is set to the proper value
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefRebuildSetting
Title  Opened and uncommented Scopes can impact simulation performance. This check identifies Scope block, Floating Scope block, and Scope Viewer. Scope Viewer does not support commenting out.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyScopes
Title  Identify active instrumentation settings on the model. This setting can cause slow simulations due to range collection.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.IdentifyActiveMMO
Title  Check for virtual bus across model reference boundaries
TitleID  mathworks.design.CheckVirtualBusAcrossModelReference
Title  Check model for parameter initialization and tuning issues
TitleID  mathworks.design.ParameterTuning
Title  Check structure parameter usage with bus signals
TitleID  mathworks.design.MismatchedBusParams
Title  Check for large number of function arguments from virtual bus across model reference boundary
TitleID  mathworks.design.CheckVirtualBusAcrossModelReferenceArgs
Title  Set Target Device and Synthesis Tool for HDL code generation
TitleID  com.mathworks.HDL.SetTargetDevice
Title  Set target reference design options
TitleID  com.mathworks.HDL.SetTargetReferenceDesign
Title  Set target interface for HDL code generation
TitleID  com.mathworks.HDL.SetTargetInterface
Title  Set target interface for HDL code generation
TitleID  com.mathworks.HDL.SetTargetInterfaceAndMode
Title  Check model for algebraic loops
TitleID  com.mathworks.HDL.CheckAlgebraicLoop
Title  Check model for unsupported blocks
TitleID  com.mathworks.HDL.CheckBlockCompatibility
Title  Check model for global sample time settings
TitleID  com.mathworks.HDL.CheckSampleTime
Title  Check model compatibility with FPGA-in-the-Loop
TitleID  com.mathworks.HDL.CheckFIL
Title  Check model compatibility with USRP(R) workflow
TitleID  com.mathworks.HDL.CheckUSRP
Title  Generate RTL code and testbench for the selected subsystem
TitleID  com.mathworks.HDL.GenerateHDLCodeAndReport
Title  Generate RTL code and IP core for embedded system
TitleID  com.mathworks.HDL.GenerateIPCore
Title  Generate RTL code and top level wrapper for the selected subsystem
TitleID  com.mathworks.HDL.GenerateRTLCode
Title  Identify similar functional clones and replace them with links to library blocks
TitleID  com.mathworks.Simulink.CloneDetection.IdentifyStructFunctionalClones
Title  Check relative execution orders for Data Store Read and Data Store Write blocks
TitleID  com.mathworks.sorting.datastorecheck
Title  Check for relative execution order change for Data Store Read and Data Store Write blocks
TitleID  com.mathworks.sorting.datastoresimrtwcmp
Title  Check if model with referenced models can be built in parallel with optimal settings.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckModelRefParallelBuild
Title  Use circular buffer to improve simulation speed for Delay blocks with large states.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckDelayBlockCircularBufferSetting
Title  Simulation might slow down if all these conditions exist: (1) the model is using a variable step solver, (2) the model contains both continuous and discrete rates, and (3) the fastest discrete rate that does not impact continuous integration is relatively smaller than 'Max step size' determined by the solver. Setting 'DecoupledContinuousIntegration' parameter to 'on' might speed up simulation.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckIfNeedDecoupleContDiscRates
Title  Simulation might slow down if all these conditions exist: (1) the model is using a variable step solver, (2) the model contains blocks having zero-crossings and continuous states, and (3) some zero-crossings are not impacting continuous integration. Setting 'MinimalZcImpactIntegration' parameter to 'on' might speed up simulation.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckIfNeedOptimalSolverResetCausedByZc
Title  Check discrete signals driving derivative port
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckDiscDriveContSignal
Title  The selection of an explicit or implicit solver depends on the approximation of the model stiffness at the beginning of the simulation. If the model represents a stiff system, use the ode15s solver. Otherwise, use the ode45 solver.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.SolverTypeSelection
Title  Adjust co-simulation settings for better performance and accuracy.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckMultiThreadCoSimSetting
Title  Identify co-simulation signals that may need explicit numerical compensation.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckNumericCompensationCoSimSetting
Title  Adjust dataflow domain settings for better performance.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckDataflow
Title  Changing simulation mode can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationModesComparison
Title  Running with compiler optimizations turned on can improve simulation speed.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.CheckSimulationCompilerOptimization
Title  Validate the overall performance improvement in your model using this check. If performance is worse than baseline, Performance Advisor discards all changes and loads the original model.
TitleID  com.mathworks.Simulink.PerformanceAdvisor.FinalValidation
Title  Check Delay, Unit Delay and Zero-Order Hold blocks for rate transition
TitleID  mathworks.design.ReplaceZOHDelayByRTB
Title  Check bus signals treated as vectors
TitleID  mathworks.design.BusTreatedAsVector
Title  Check for potentially delayed function-call block return values
TitleID  mathworks.design.DelayedFcnCallSubsys
Title  Identify block output signals with continuous sample time and non-floating point data type
TitleID  mathworks.design.OutputSignalSampleTime
Title  Check usage of Merge blocks
TitleID  mathworks.design.MergeBlkUsage
Title  Check usage of Outport blocks
TitleID  mathworks.design.InitParamOutportMergeBlk
Title  Check usage of Discrete-Time Integrator blocks
TitleID  mathworks.design.DiscreteBlock
Title  Check model settings for migration to simplified initialization mode
TitleID  mathworks.design.ModelLevelMessages
Title  Check model for custom library blocks that rely on frame status of the signal
TitleID  mathworks.design.DSPFrameUpgrade
Title  Check solver configuration
TitleID  com.mathworks.hdlssc.ssccodegenadvisor.checkSolverConfigurationTask
Title  Check switched linear
TitleID  com.mathworks.hdlssc.ssccodegenadvisor.checkSwitchedLinearTask
Title  Discretize equations
TitleID  com.mathworks.hdlssc.ssccodegenadvisor.discretizeTask
Title  Generate implementation model
TitleID  com.mathworks.hdlssc.ssccodegenadvisor.generateImplementationModelTask
Title  Check for large matrix operations
TitleID  com.mathworks.HDL.ModelAdvisor.runMatrixSizesChecks
Title  Check for blocks that have nonzero output latency
TitleID  com.mathworks.HDL.ModelAdvisor.runNFPLatencyChecks
Title  Check algebraic loops
TitleID  com.mathworks.HDL.ModelAdvisor.runAlgebraicLoopChecks
Title  Check for double datatypes in the model with Native Floating Point
TitleID  com.mathworks.HDL.ModelAdvisor.runDoubleDatatypeChecks
Title  Check for Data Type Conversion blocks with incompatible settings
TitleID  com.mathworks.HDL.ModelAdvisor.runNFPDTCChecks
Title  Check for HDL Reciprocal block usage
TitleID  com.mathworks.HDL.ModelAdvisor.runNFPHDLRecipChecks
Title  Check for Relational Operator block usage
TitleID  com.mathworks.HDL.ModelAdvisor.runNFPRelopChecks
Title  Check for single datatypes in the model
TitleID  com.mathworks.HDL.ModelAdvisor.runNFPSuggestionChecks
Title  Check for unsupported blocks with Native Floating Point
TitleID  com.mathworks.HDL.ModelAdvisor.runNFPSupportedBlocksChecks
Title  Check for large matrix operations
TitleID  com.mathworks.HDL.ModelChecker.runMatrixSizesChecks
Title  Check for blocks that have nonzero output latency
TitleID  com.mathworks.HDL.ModelChecker.runNFPLatencyChecks
Title  Check algebraic loops
TitleID  com.mathworks.HDL.ModelChecker.runAlgebraicLoopChecks
Title  Check for double datatypes in the model with Native Floating Point
TitleID  com.mathworks.HDL.ModelChecker.runDoubleDatatypeChecks
Title  Check for Data Type Conversion blocks with incompatible settings
TitleID  com.mathworks.HDL.ModelChecker.runNFPDTCChecks
Title  Check for HDL Reciprocal block usage
TitleID  com.mathworks.HDL.ModelChecker.runNFPHDLRecipChecks
Title  Check for Relational Operator block usage
TitleID  com.mathworks.HDL.ModelChecker.runNFPRelopChecks
Title  Check for single datatypes in the model
TitleID  com.mathworks.HDL.ModelChecker.runNFPSuggestionChecks
Title  Check for unsupported blocks with Native Floating Point
TitleID  com.mathworks.HDL.ModelChecker.runNFPSupportedBlocksChecks
Title  Check for non-continuous signals driving derivative ports
TitleID  mathworks.design.NonContSigDerivPort
Title  Check data store block sample times for modeling errors
TitleID  mathworks.design.DataStoreBlkSampleTime
Title  Check for potential ordering issues involving data store access
TitleID  mathworks.design.OrderingDataStoreAccess
Title  Check virtual bus inputs to blocks
TitleID  mathworks.design.VirtualBusUsage
Title  Check for root outports with constant sample time
TitleID  mathworks.design.CheckConstRootOutportWithInterfaceUpgrade
Title  Check model for S-function upgrade issues
TitleID  mathworks.design.CheckForSFcnUpgradeIssues
Title  Identify unit mismatches in the model
TitleID  mathworks.design.UnitMismatches
Title  Identify automatic unit conversions in the model
TitleID  mathworks.design.AutoUnitConversions
Title  Identify disallowed unit systems in the model
TitleID  mathworks.design.DisallowedUnitSystems
Title  Identify undefined units in the model
TitleID  mathworks.design.UndefinedUnits
Title  Identify ambiguous units in the model
TitleID  mathworks.design.AmbiguousUnits
Title  Check model for block upgrade issues requiring compile time information
TitleID  mathworks.design.UpdateRequireCompile
Title  Identify questionable operations for strict single-precision design
TitleID  mathworks.design.StowawayDoubles
Task Name  Simulation Accuracy
Task Name  Simulation Runtime Accuracy Diagnostics
Task Name  Managing Data Store Memory Blocks
Task Name  Simulink Model File Integrity
Task Name  S-function Checks
Task Name  Units Inconsistencies
Task Name  Modeling Signals and Parameters using Buses
Task Name  Modeling Single-Precision Systems
Task Name  Migrating to Simplified Initialization mode
Task Name  Model Referencing
Task Name  Managing Library Links And Variants
Task Name  Data Transfer Efficiency
Task Name  Upgrading to the Current Simulink Version